Task in verilog code

I am using task in my module in verilog coding, and facing problem, in passing the argument values. actually The variables defined in the task block as input are not receiving the values that are passed to them while calling this task. Here is the code

module carry_addr(Cin,A,B,Sum, Cout,rst_n ); parameter width=3; parameter bits=1; input [width:0] A,B; input Cin,rst_n; output reg [width:0] Sum; output reg Cout; integer k;

reg [width+1:0]C2;

task fulladder; input A1; input B1; input C4; output reg Sum1; output reg C0; begin

    Sum1=0;
    C0=0;
  {C0,Sum1}=A1+B1+C4;

end endtask

task automatic ripple; input [bits:0] A2; input [bits:0] B2; input C1; output reg [bits:0]sum2; output reg cout; reg [bits:0]sum3,sum4;

reg [bits+1:0] C,C3; begin

        sum2=0;
        sum3=0;
        sum4=0;
       cout=0;
        C=0;
        C3=0;

        C[0]=0;     
        C3[0]=1;
        for (k=0;k<=bits;k=k+1)
        begin 
             fulladder(A2[k],B2[k],C[k],sum3[k],C[k+1]);
             fulladder(A2[k],B2[k],C3[k],sum4[k],C3[k+1]);

        end
        if(C1==0)
        begin
            cout=C[bits+1];
            sum2=sum3;
        end
        else if(C1==1)
        begin
            cout=C3[bits+1];
            sum2=sum4;
        end

end endtask

always@(rst_n or A or B or Cin) begin if(!rst_n) begin Sum=0; Cout=0; C2=0; end

     C2[0]=Cin;
     for (k=0;k<=width;k=k+bits+1)
     begin
          ripple(A[k+:bits],B[k+:bits],C2[k],Sum[k+:bits],C2[k+bits+1]);

     end
     Cout=C2[width+1];

end

endmodule

in this specifically, A,B 's values are not copying in the A2,B2 variables in the ripple task.