Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.
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Verilog: Data Transfer using inout ports
I have an EEPROM following I2C protocol. My write operation was fine. While a read operation, SDA being my inout pin, during data transfer from slave, I held the pin in high impedance (Z).I received ...
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Verilog: I2C read operation
In a verilog simulation, I will have to communicate with the 64K I2C EEPROM from Microchip. Every time for getting an ack from slave, I am driving my SDA to high impedance for a given clock period. ...
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91 views
My design is not meeting timing. What can I do?
I am using the Altera Quartus II software to compile Verilog for a Cyclone IV FPGA. In my case, the FPGA is fixed; I cannot get a faster one.
Now one isolated module in my design, which deals with ...
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Verilog - Referencing Flattened Busses in Module Instantiation
I have a verilog gate-level netlist generated by Synopsys Design Compiler.
DC was directed to flatten all busses and ports when creating the netlist, and the module declaration is given below:
...
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Inferring BUFGMUX in Xilinx FPGAs for Clock Multiplexing
I have a VHDL memory core which requires me to multiplex between two clocks. The Write clock operates at 200 Mhz and Read clock operates at 100 Mhz. I think this can be done using BUFGMUX (correct me ...
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78 views
Why does changing an 'add' to a logical or devour 7 CPLD macrocells?
I have a design that's synthesizing to about 50 macrocells.
I have this section of code:
module levers2(
input [2:0] LL,
input [2:0] RL,
output reg [10:0] DIVISOR,
output reg FAULT
...
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82 views
“is not declared” error in Verilog
I created a simple 8-3 encoder module (called encoder8to3) to replace a few repeated instances of Verilog code. I then tried to use the module in levers2.v. I get the following error when I run a ...
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Multi-Port RAM (1 write port, many read ports)
I have a project where I may need a 128 KB lookup RAM. I have 1 write port which writes the lookup values at the start of the application. I will have more than 2 read ports (I am assuming 4). I do ...
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Verilog - A line stays high, I need it to go low after a while
I'm working on a circuit in Verilog to be implemented on a CPLD. The output of the circuit will drive a stepper motor. The input is a stream of pulses from a machine.
I generate a stepper pulse ...
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1answer
66 views
Verilog design decision - where should my counter be located?
I am coding in Verilog a typical count-to-n-then-reset-to-0 counter. My module has the logic to increment and reset the counter.
My issue is that I don't know where the counter itself should be ...
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48 views
Using Xilinx ISE tools, “does not have a port named” error
I'm a verilog Beginner.
I created a design using straight-up Verilog then tested it using the ISE design tools. Works great.
I would like to synthesize this to see the resources that will be ...
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Looking for a program that can simulate a Verilog HDL file
I was wondering whether a program has been made that can simulate the end product of a Verilog HDL design file.
To give some information I am using Quartus 2 (the design file is a verilog HDL file) ...
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163 views
What is clock skew, and why can it be negative?
My HDL compiler (Quartus II) generates timing reports. In it, the nodes have "clock skew" column. The only definition of clock skew I found is in the TimeQuest documentation (see page 7-24):
To ...
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4answers
188 views
Using both edges of a clock
I am programming an Altera Cyclone IV using Verilog and Quartus II. In my design, I would like to use both edges of a clock so that I can do clock division by an odd factor with a 50% duty cycle. Here ...
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111 views
Generate an n bit random number in Verilog
I can easily generate a random number of width 32 bits in Verilog using $random. Is there a way to generate a random number of exactly n bits (say n = 70)?
I guess I could concatenate many 32-bits ...
