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Now that I'm going to be using the PSoC 5 as my microcontroller of choice, I would like to learn Verilog so I can create my own peripherals for it.

I have spent some time searching the web for Verilog learning resources (especially ASIC World), and I feel I've learned quite a few things about it, however, I also feel that there's a big hole in my understanding. This is because there is something that none of the resources seem to teach.

Once I know the syntax, how do I go about designing a Verilog peripheral?

What I mean is, I'm still baffled by the designs people create in Verilog. E.G. Why did they do it that way, not the obviously much simpler way? For example, I came across this code:

task add;      // task definition
 input a, b;   // two input argument ports
 output c;     // one output argument port
 reg R;        // register declaration
 begin
   R = 1;
   if (a == b)
     c = 1 & R;
   else
     c = 0;
 end
endtask

There must be a good reason for the design, but it seems bizarre to me. I get the syntax, I see what it does, but I don't understnd why. Is there some resource for learning to think in Verilog?

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No one would really write such code. Specifically R is always 1 so it and "& R" aren't useful. – Brian Carlton Apr 10 '12 at 19:09

5 Answers

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+50

MIT Opencourseware 6111 is a free online course about digital systems.

The syllabus says:

On completion of 6.111 students will have confidence in their abilities to conceive and carry out a complex digital systems design project in a team of two or three people. More broadly, they will be ready to handle substantial, challenging design problems. In particular, students will be able to:

  1. explain the elements of digital system abstractions such as digital logic, Boolean algebra, flip-flops, finite-state machines (FSMs), and microprogrammed systems. design simple digital systems based on these digital abstractions,and the "digital paradigm" including discrete, sampled information.
  2. use basic digital tools and devices such as digital oscilloscopes, PALs, PROMs and VHDL.
  3. work in a design team that can propose, design, successfully implement, and report on a digital circuit design project.
  4. communicate the purpose and results of a design project in written and oral presentations.

That course does use VHDL rather than Verilog, but the why for both languages is the same and all tasks could be implemented in either language.

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Fantastic, thanks! – Rocketmagnet Apr 13 '12 at 14:38
FYI the 2006 version of the course is Verilog-based. – compumike Jul 26 '12 at 1:23
up vote 2 down vote

If you want to think in Verilog, it is better to think of Verilog as a description of the hardware you want to design rather than as describing a sequence of steps to be executed. To do that you need to think in terms of how your Verilog code will be translated into circuits, which is the domain of digital design.

Most University EE departments require digital design as a sophomore level class. Now that places like Stanford and MIT are putting course materials online you may be able to find notes and exercises that way.

I tend to find textbooks more cohesive than trying to search through lots of web sites. There are many digital design text books out there -- some good and some bad. One of my favorite books is Digital Design Principles and Practices by John Wakerly. In addition to theory, Wakerly includes lots of practical information based on years of experience in digital design.

When you get to a point where you want to look at code, try OpenCores. As with any collection of open source projects, some are great and others could use more work. You can generally pick out the higher quality ones based on activity and comments.

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up vote 1 down vote

I think that this code snippet is just that - a snippet of code that shows all the features of a particular language feature (calling tasks) but doesn't really do anything useful

But one take away that may not be obvious in this snippet is that the parameters and R have lifetimes beyond that of the function call - unlike say C in Verilog if you call the task again the 'local' variable R will have the value you left it with last time you called it - it's easy to think of verilog variables this way: in real world logic you can't just create storage on the stack, everything has to be able to be statically created when the design is created (there are a few places where this is not true, usually features added later to the language)

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Thanks for the answer. The code snippet was only meant to illustrate one of the many things which I don't understand, including whole peripherals implemented in Verilog. What I'm really looking for is a good learning resource about designing peripherals in Verilog. – Rocketmagnet Feb 6 '12 at 21:06
up vote 1 down vote

I used fpga4fun.com to learn the basics of Verilog and found it to be an excellent resource with simple and well documented examples. I like the fact that the examples are for the kinds of tasks that you would typically do on an FPGA or CPLD, as long as you are not in the business of designing CPUs.

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up vote 0 down vote

The bounty on this has already been selected (along with the best answer), but I'll add what I just found.

I've found a free e-book for learning VHDL written for people that basically have at least some amount of traditional programming experience, but no HDL experience. It's called Free Range VHDL and I've just began reading it and it really makes sense to me. And I'm pretty sure that once you learn one HDL, it'll be a lot easier to learn another HDL(such as Verilog)

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