I was wondering whether a program has been made that can simulate the end product of a Verilog HDL design file.
To give some information I am using Quartus 2 (the design file is a verilog HDL file) and compiling it, (and then I would download the design to an Altera DE2 board (Cyclone II). I am asking whether a program exists that would allow me to do this without the physical DE2 board).
For example, a Verilog HDL file that takes switches as inputs and outputs are seven-segment displays.
I hope I have used the correct terminology as I am new to coding in Verilog.
Any suggestions welcome :)
