Thread: [Doxygen-users] VHDL packages and links to types

Is there any way I can link to types defined in packages from my mainpage
VHDL file or from other entities?

I have tried apackage#atype, apackage.atype, apackage::atype
and apackage:atype but none of these works...?

/Carsten

try this example

package standard is 

	type boolean is (false,true); 

	type bit is ('0', '1'); 

end package;


--!\mainpage my project
--! @see standard::bit


Carsten Jørgensen-2 wrote:
> 
> Is there any way I can link to types defined in packages from my mainpage
> VHDL file or from other entities?
> 
> I have tried apackage#atype, apackage.atype, apackage::atype
> and apackage:atype but none of these works...?
> 
> /Carsten
> 
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