This cite uses an automatic for matter for code. For example VHDL. Questions about it belong here.
2
votes
0answers
49 views
Assembly and Basic syntax highlighting
I request the feature of syntax highlighting Assembly and Basic code. As W5VO said, we don't have it yet. However, Assembly is used regularly on this site. And while we're at it, why not add Basic as ...
3
votes
1answer
34 views
lang-none specifier only works in preview
This question uses an ASCII diagram and has the verilog tag.
To avoid syntax highlighting, I used the <!-- language: lang-none --> directive. Per the SO ...
5
votes
0answers
95 views
Do we need a custom Verilog syntax highlighter?
Verilog is a C-like language. It uses a similar layout, has equivalent control keywords, and highlights OK when using the C syntax highlighter:
Of course, it has some notable differences, including ...
13
votes
1answer
151 views
Support VHDL syntax highlighting
We now have syntax highlighting for a host of languages through Google Prettify. Regrettably, the default set:
...
7
votes
1answer
68 views
Syntax highlighting should be supported on Electrical Engineering, like on SO
I thought based on this MSO question, it might be that syntax highlighting is supported here, as people rarely tag their questions with the appropriate language, so the highlighter might go into ...
