Automating test vector in Verilog HDL

Question

This is my first attempt at learning Verilog HDL testbench for an AND gate:

   '
   ' 
initial
   begin
  //case 0
  A_t <= 0; B_t <= 0;
  #1 $display("F_t = %b", F_t);

  //case 1
  A_t <= 0; B_t <= 1;
  #1 $display("F_t = %b", F_t);

  //case 2
  A_t <= 1; B_t <= 0;
  #1 $display("F_t = %b", F_t);

  // case 3
  A_t <= 1; B_t <= 1;
  #1 $display("F_t = %b", F_t);

  end
endmodule

My question is since this is for a two input we had only four test cases, lets say we have 2000 cases, then can we use a for loop as shown below:

   '
   '
initial
  begin
 for (i=0;i<2000;i++)
{
 for (j=0;j<2000;j++)
 {
A_t <= i; B_t <= j;
  #1 $display("F_t = %b", F_t);
 }
}
  end
 endmodule

Is this legally correct to use loops like this? If not then please suggest me the correct method for automating the inputs.

pjc50 · Accepted Answer · 2012-12-17 10:13:26Z

'for' loops exist in verilog, but they look like this:

for(i = 0; i < 2000; i = i + 1) begin
 A_t <= i;
 #1 $display("F_t = %b", F_t);
end

There is no ++ operator and you have to use begin and end.

It's a very reasonable way of automating the inputs. Of course you have to get the timing right, which in your case is done with that #1 there.

Tomas · Answer 2 · 2012-12-17 10:14:41Z

It is a quite good approach since the testbench isn't supposed to be synthesised. (Small syntactic changes still has to be made as suggested by the previous answer)

You can also extend the testbench by having the test vectors in an external file, that would make it more flexible.

Another solution would be to use do-files for modelsim and generate stimuli that way.

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Automating test vector in Verilog HDL

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