ALU implementation in Verilog: how to handle negative numbers?

I am designing a simple ALU with and, add, load operations for 16-bit inputs. This is what I have so far:

module ALU(overflow,out,in1,in2,select); 
input[1:0] select;
output[15:0] out;
output overflow;
reg[16:0] out;
reg overflow;
always @(in1,in2,select)

case(select)           

   0:out <= in1 & in2;    //and

   1:{overflow,out} <= in1 + in2;    //add

   2:out <= in1;         

   default: out<= 16'bx;

endcase                    
endmodule

I am confused how to deal with negative numbers and how to handle when my inputs are negative: what should I do?