Tagged Questions
25
votes
6answers
924 views
Readable and educational implementations of a CPU in a HDL
Can you recommend a readable and educational implementation of a CPU in VHDL or Verilog? Preferably something well documented.
P.S. I know I can look at opencores, ...
14
votes
7answers
1k views
Can an FPGA design be mostly (or completely) asynchronous?
We had a very short FPGA/Verilog course at university (5 years ago), and we always used clocks everywhere.
I am now starting out with FPGAs again as a hobby, and I can't help but wonder about those ...
12
votes
1answer
564 views
How is ASIC design different from FPGA HDL synthesis?
I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA.
I've ...
9
votes
8answers
1k views
Newbie projects on an FPGA?
I'm two weeks away from completing my first college digital logic design course, and apparently there isn't going to be a final project--just a tedious final exam.
So as any curious student would ...
6
votes
4answers
608 views
Different Adder Implementations
I'm putting together an ALU, that I want to synthesize on an FPGA. The carry-look-ahead adder is the one many choose to use as opposed to the ripple-carry adder. However, a thought crossed my mind. ...
5
votes
2answers
362 views
Beginner with fpga and timing issues
I got myself a spartan-3an evaluation board in order to learn fpga programming and some verilog. It's taken a little while to stop seeing it in terms of a sequential programming language and to start ...
4
votes
5answers
290 views
Stress testing an FPGA's power supply
I have an FPGA (Xilinx Spartan 6) for which I want to stress test the power supply in "steps" (e.g. the FPGA runs in loops of 1 seconds: full steam for 900 ms, halted for 100 ms) to check that the ...
4
votes
4answers
914 views
Using both edges of a clock
I am programming an Altera Cyclone IV using Verilog and Quartus II. In my design, I would like to use both edges of a clock so that I can do clock division by an odd factor with a 50% duty cycle. Here ...
4
votes
3answers
1k views
What is clock skew, and why can it be negative?
My HDL compiler (Quartus II) generates timing reports. In it, the nodes have "clock skew" column. The only definition of clock skew I found is in the TimeQuest documentation (see page 7-24):
To ...
4
votes
1answer
95 views
Difference between @* and @(*) in verilog
What is the difference between always @* and always @(*) in verilog?
4
votes
3answers
311 views
Help wanted explaining signals coming with higher frequency than clock and how to handle them
I am getting my hands on Verilog and FPGA programming. So I wrote a simple module that handles two inputs - button signal and a clock. Initially, it lights up two LEDs and when the user presses and ...
4
votes
2answers
188 views
Flip-flop vs combinatorial description - what exactly is the difference?
I was going through some reference design from Altera's Wiki and ran into the following piece of code:
...
4
votes
3answers
219 views
LUT vs. hard IP based multipliers on Spartan-3 FPGA for constant coefficient multiplication
Before I get to my question, here are the specs for the board and synthesis tool I am using:
Family: Spartan3
Device: XC3S200
Speed: -5
Synthesis Tool: XST
My 4-bit multiplier is in my design's ...
4
votes
2answers
220 views
how to implement a low pin count stereo display (FPGA)
I need to design a TX/RX pair which functions like a HDMI 1.4 3D, for a proprietary HUD. The source signals are 2 distinct TFT output in RGB， and the sinks are also two separate OLEDs, and a stereo ...
4
votes
0answers
92 views
Minimal redistributable coregen output for command-line rebuilds
I'm building an SoC with my own soft-core, and I want people to be able to easily rebuild it using Xilinx webpack command-line tools. I'm using coregen's Clock Wizard to create a clock module, but ...
