Tagged Questions
4
votes
1answer
98 views
Is there an FPGA based vector graphics card project?
I have been messing around with VGA projects as my latest interest. I have a Xilinx Spartan 3E 250K FPGA, which has just barely too little RAM for a full 640x480 frame buffer. So, I'm looking at ...
1
vote
1answer
117 views
Improve my “From NAND to Tetris” ALU in VHDL
I'm following the course From NAND to Tetris, but instead of using the author's software, I'm trying to directly program a Spartan 6 FPGA. I'm now solving the ALU exercise, and ended up writing the ...
0
votes
1answer
67 views
VHDL: logical block 'dcm' with type 'DCM_BASE' could not be resolved
I keep getting the following error when I go to implement my design in Xilinx ISE:
...
1
vote
1answer
61 views
Interfacing SJA1000 to Spartan6 FPGA
As the title says, I would like to interface an SJA1000 CAN controller to a Xilinx Spartan6 FPGA.
The SJA1000 has a shared 8-bit address&data bus with an address latch signal and either separate ...
0
votes
3answers
178 views
Vhdl VGA Problem
I'm doing a fpga project in vhdl for my studies.
I'm displaying a dog on the screen that I try to move. That works well for right, left and up but trying to make the dog go down, it moves in a ...
4
votes
1answer
95 views
Difference between @* and @(*) in verilog
What is the difference between always @* and always @(*) in verilog?
2
votes
3answers
145 views
about the code for fir filter
Below is a 4 tap filter. That means the order of the filter is 4 and so it has 4 coefficients. the input is signed type of 8 bits wide. The output is also of signed type with 16 bits width. The ...
8
votes
1answer
309 views
MD5 VHDL pipeline
I am trying to implement a 3-stage MD5 pipeline according to this link. In particular the algoritms on page 31. There is also another document which describes data forwarding. This is done in an FPGA ...
2
votes
3answers
175 views
Using signal in different modules vhdl
I am trying to connect a microcontroller(cortex m3) and a fpga(actel a3p060). I am able to read/write successfully with 16 bit databus. My modules in vhdl is structured as follows:
Top ...
1
vote
4answers
155 views
In which cases should I use Z as output in HDL?
I created a simple multiplexer which feeds different input into output depending on statemachine.
Now there are states when I do not need the output so I usually set it to 0.
...
3
votes
1answer
289 views
4
votes
2answers
374 views
Why not SRAM for FPGA in image processing?
I'm beginning with VHDL coding and I've done some basic image processing on my development board.
I've noticed that most FPGA development boards often use DRAM (SDRAM, DDRAM) as RAM.
For example, I'm ...
4
votes
1answer
101 views
8
votes
4answers
493 views
FPGA firmware design: How big is too big?
I have a particularly large signal processing transform that needs to be ported from matlab to VHDL. It definitely requires some kind of resource sharing. A bit of calculation gave me the following:
...
-1
votes
2answers
126 views
Need Quartis II CPLD tutorial for learning VHDL from ZERO [closed]
I am learning VHDL from zero using Altera CPLD. Already got Quartis II 12.1 and a 15-lines example VHDL (like Hello World for C learner).
To avoid learning bad coding style or digging too deep too ...
