The cpu-architecture tag has no wiki summary.
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Unable to run on device - unsupported architecture error
all.
I was wondering if someone could help me with my problem. I have a project that I'm working on. I have all the certificates and necessary profiles in place, or at least I’m pretty sure. The ...
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how do you find the sizeof address and data bus
Recently I saw that this is a question which is asked in an interview.
how do you find the sizeof address and databus in a system.
You can find the sizeof address using sizeof for a pointer.
But ...
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How does direct mapped cache work?
I am taking a System Architecture course and I have trouble understanding how a direct mapped cache works.
I have looked in several places and they explain it in a different manner which gets me even ...
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How to use Fused Multiply-Add (FMA) instructions with SSE/AVX
I have learned that some Intel/AMD CPUs can do simultanous multiply and add with SSE/AVX: FLOPS per cycle for sandy-bridge and haswell SSE2/AVX/AVX2.
I like to know how to do this best in code and I ...
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Cache behaviour of memory-mapped I/O
Does anyone know which type of CPU cache behaviour (e.g. uncacheable write-combining) is assigned to file-backed, memory-mapped I/O on modern x86 systems? Is there any way to detect which is the ...
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What is this technical term? Processing and Architecture related. Rush to “X” [closed]
So I remember reading this term a while ago.
Basically, it was that if you had a processor, it was always better to finish your task as fast as possible and then idle/power off, rather than slow down ...
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1answer
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State machine event generation in multi-processor architecture
I'm having a small architecture argument with a coworker at the moment. I was hoping some of you could help settle it by strongly suggesting one approach over another.
We have a DSP and Cortex-M3 ...
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Program Counter and Instruction Register
Program counter holds the address of the instruction that should be executed next, while instruction register holds the actual instruction to be executed. wouldn't one of them be enough?
And what is ...
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What is difference between sjlj vs dwarf vs seh?
Well, that's all. I can't find enough information to decide which compiler should I use to compile my project. There are several programs on different computers simulating a process. On Linux I'm ...
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1answer
173 views
FLOPS per cycle for sandy-bridge and haswell SSE2/AVX/AVX2
I'm confused on how many flops per cycle per core can be done with Sandy-Bridge and Haswell.
As I understand it with SSE it should be 4 flops per cycle per core for SSE and 8 flops per cycle per core ...
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1answer
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XMM Registers Total or Per Core
In a multicore CPU, does each core have access to it's own bank of XMM registers? For example if a chip is listed as having 16 XMM registers (XMM0-XMM15), is that 16 registers per core or 16 shared?
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How would you generically detect cache line associativity from user mode code?
I'm putting together a small patch for the cachegrind/callgrind tool in valgrind which will auto-detect, using completely generic code, CPU instruction and cache configuration (right now only x86/x64 ...
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CPU operations during g++ compiling
I would like to invest in a build server to decrease the time of g++ compilation.
Since the sources are parallelizable, our idea is a many-core system. (32-48-64 cores)
My question is that what type ...
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1answer
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Designing ALU Control block for single cycle MIPS
Hope this isn't off topic for Stack Overflow.
I was learning about MIPS and I've gotten stuck at this step. This is the truth table for the ALU Control Block.
Now this is the first time I'm coming ...
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Resource Dependencies between processes
Given processes are :
P1: C=D * E
P2: M=G + C
P3: A=B + C
P4: C=L + M
P5: F=G + E
The processes are assumed to be single statements for simplicity.
Resource Dependence is concerned with ...
