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Is something like this possible ? I basically need a variable to control the width of the right hand side. I am planning to use this in an test bench where I just have to change the parameter width at the beginning of the file, and this parameter sets the net width in all other occurrences of 'a_net'. If this doesn't work - is there any other workaround ? |
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You want to match the right hand side width with the declaration width to avoid tool warnings? First use a 1-bit wide zero constant, this will be expanded using the Verilog expansion rules, which will give you an appropriate width zero: If that generates a simulator/synthesiser warning your tools are outside of the Verilog spec. A common way to get around this is with the replication operator, which can take a constant width: |
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You can do this with parameters is you want it just in one module: For more than one module it's easier to do it with a define: |
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