Digital electronics use a finite number of states, unlike analog electronics that treat continuous signals. Digital logic is used to perform arithmetic operations with electric signals, and constitutes the base for building CPUs.
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votes
1answer
40 views
Turn S R Latch Using a NOR gates into NAND
I can't post a picture so the question will use Boolean Algebra. For me an SR Latch is
S NOR Q' = Q
R NOR Q = Q'
I will represent Q' as P since Q' might be ...
0
votes
0answers
19 views
Resource for learning Digital Electronics [closed]
I would like to learn Digital Electronics(Boolean Algebra,GATES,K-Map,GreyCode,SHIFT registers,FLIP FLOPS).
Would you recommend resources similar to Murach's Book Series or Head First Series.
-3
votes
1answer
64 views
What is Block diagram? [closed]
I have to design a simple 8 bit processor with VHDL and the first step is to draw a single or schematic block diagram including registers, arithmetic operations, multiplexers, busses and control ...
0
votes
1answer
39 views
Adding 4-bit numbers to 16-bit shift register
I am trying to find a way to add four 4-bit binary numbers to a 16-bit shift register, one(group of 4 bits) by one. This way I can store 4 decimal numbers(0-9) in the register, adding them by pushing ...
0
votes
1answer
59 views
Sequential logic counters
I have an assignment to create a counter that counts in the following way depending on input y
if y = 0 -> 0, 6, 3, 2, 1, 0...
if y = 1 -> 0, 5, 4, 7, 2, 1, 0...
Also it has another input x if x = ...
1
vote
1answer
50 views
How to calculate Gate Delays in normal Adders and Carry Look Ahead Adders
In my textbook the gate delays for the n-bit ripple adder is given as \$ 2n \$ for \$c_n\$ bits and \$ 2n-1 \$ for \$ s_n-1 \$ for the circuit as shown below:
But, for a 4-bit Carry Look Ahead ...
1
vote
3answers
53 views
How do I decide the bandwidth of a driver through 'input transition rise and fall rate'?
I am carrying out a design with a driver:74LVC1G125 datasheet of 74LVC1G125. Signal that will go through this driver is about 600khz so I have to know the bandwaidth of 74LVC1G125. I have read the ...
3
votes
4answers
49 views
N-Ch FET with open-drain output
I stumbled across this line in this datasheet (page 10):
Serial Data Output Pin. Internal N-Ch FET with open-drain output that
requires external pull-up resistor. It shifts out the previous ...
0
votes
1answer
88 views
Circuit design example
What will a combinational logic circuit look like using any basic gates having the output=1 when the input=110 and 101?
1
vote
2answers
43 views
Parameterized net width in Verilog
Is something like this possible ?
parameter width;
wire[width-1] a_net = (width)'b0;
I basically need a variable to control the width of the right hand side. I ...
1
vote
2answers
121 views
Instruction Register? Whats it's purpose/how is it connected? (And what happens after)
So im learning the SAP 1 Computer Architecture. Most things I get pretty well, but from what I understand: (Lets pretend it's an 8bit and address is 4 bits and opcode is 4bit)
...
4
votes
3answers
91 views
FPGA Logic Gate Count
I found an FPGA board that I liked. It uses a Xilinx Spartan 6 LX45. When I went to the datasheet for the Spartan 6 series, it only said that there were 43,661 logic cells. How many gates does that ...
1
vote
1answer
69 views
Problem with the 74160 decade counter
As I am experiencing with different TTL components, I am having a ton of trouble with the 74160 decade counter. I don't know if it's my inexperience or if I'm dealing with a malfunctioning IC, but the ...
3
votes
1answer
129 views
Improving a Push-Button Debouncing Circuit
I'm having problems testing a 7490 decade counter, the switch sometimes toggles 2 or 3 counts (it's a pushbutton). This is already using this debouncing circuit I found:
(well great, I can't post ...
1
vote
1answer
39 views
Technology mapping
The function given is:
g=ACFG + ADEG + DHJ + BCFI
and i am asked to perform the reconverge theorem on this function which means taking all possible pairs of LUT that share the same input merge them ...
2
votes
1answer
52 views
Optimal Solution for function using Distributed Law [closed]
I was given the function:
\$ h = 𝐴.𝐵' + 𝐶 + 𝐵.𝐶'.𝐷 + 𝐵.𝐸 + 𝐵'.𝐶.𝐷'.𝐹 \$
I was told to construct it in the most optimal way using only any size NOR gate by applying distributive law.
I ...
0
votes
1answer
29 views
Logisim - Tunnel that outputs the OR result of all of its inputs
Consider this screenshot:
When the two values differ, I get this:
This makes sense, but it's a problem. I would like the tunnel to function like this: when it's getting mixed values, it outputs ...
-9
votes
1answer
71 views
Circuit Diagram Controller [closed]
I want to make a circuit diagram which will:
Read the speed of a servo
Divide the speed of servo
With the result of the division will be controlled the speed of an other motor like this: Servo ...
-5
votes
0answers
64 views
Applications with kernels that can be accelerated in hardware [closed]
Could you give me a list of applications with kernels that can be accelerated in hardware?
Some examples would include FFT, AES, Motion Estimation, Viterbi Decoder. I'm just looking for others.
To ...
1
vote
4answers
97 views
What is important in computer clocks' signal: signal edges or intervals when signal is stable? Will multiple value propagation occur?
I am trying to figure out some basics of digital electronics. We have all seen the squared graph of the computer clock signal:
I have read multiple articles on the Internet and still can't figure ...
0
votes
1answer
100 views
Help designing a simple counter
I would like to create a project to implement an asynchronous counter (I am just learning about sequential circuits), in which 2 8-segment displays will receive input from some sensor and will ...
2
votes
1answer
108 views
Multiplexing large LED matrix
I have a project which involves building a 64 x 48 (3072) LED matrix driven by a Raspberry PI computer. I am a first-year computer engineering student so I am still inexperienced with shift registers ...
2
votes
2answers
63 views
Easy resource to learn solving counter problems?
Could anybody please point me some direction on where I can learn to solve simple counter problems like counting in a given sequence using a given flip-flop? For example:
Create a counter counting ...
0
votes
1answer
53 views
Using on and off switches and logic gates
So I have 2 switches Representing:
Bit A
Bit B
And then I have :
AND gate
OR gate
Not gate
Some other gates like adder and comparator
I used the method described here because the Adder & ...
-1
votes
0answers
62 views
Remappable pins [closed]
I have found myself lost on this one... I am designing a dev/backup board for one of my projects for a solar car. One of the main goals of this board is to be able to connect pin X on the input side ...
-3
votes
1answer
74 views
Building 8bits alu on breadboard [closed]
I want to build a 8 bit alu containing :
- 8 bit comparator
- 4 inverters
- 2 and gates
- 2 or gates
- 2 full adder 4 bits
- 10 leds
- 8 mux 8 to 1
e
My question is how much volt do I need to make ...
-2
votes
0answers
106 views
9v battery drain in 1 minute when connected to breadboard [closed]
I have a breadboard with 16 switch , 8 leds , 1 comparator, 2 4bit adder, 2 and gates. I connect a 9v battery through a regulator to output 5v suitable for the ICs.
the problem happen as soon as i ...
-7
votes
0answers
29 views
How to make Digital Power Meter Remote Control? [closed]
How to make Digital Power Meter Remote Control?
I want circuit diagram for Digital Power Meter Remote Control.
or Digital Power Meter circuit diagram for my engineering project
0
votes
0answers
48 views
Connecting RJ11 output to TTL to USB converter input through 5 pin TTL
I have a problem in connecting output of RJ11 to TTL socket of the TTL to USB converter.
Actually, I have a micro controller based device which has an RJ11 female port having six pins in it, which I ...
-1
votes
0answers
40 views
HD-SDI to SD-SDI
I need to convert a HD-SDI signal to SD-SDI.
I have been looking into deserializers and fpga, but have not found a good solution yet.
How can this be done?
Preferred is a "simple" solution, that ...
0
votes
3answers
91 views
Logic Circuits Vs Transistor Power Circuits
I have need to invert a signal to drive fets with hard/fast rise and fall times. I was told in another thread to use an inverter (NOT chip). This makes perfect sense to me since logic chips are ...
-6
votes
0answers
60 views
3 bit counter using d flip flops [closed]
i need to design a 3 bit counter that will increment and decrement a stored value by a 3 bit value depending on the positive edges of a signal C. Must use 3 D flip-flops. any help would be appreciated ...
0
votes
2answers
81 views
Can Transmission gates be used to implement 3 State Logic?
In my application i need to use a common line shared between two peripherals, i have to indicate to the devices whenever the bus is free or not, hence i can't have push-pull output where the output is ...
2
votes
4answers
139 views
Most efficient way to select between 10 large buses?
I need to select between 10 different 164-bit buses using four-bit BCD (8421, unsigned binary). What is the most efficient way to do so?
Currently I have the following SystemVerilog implementation
...
2
votes
1answer
65 views
In verilog, what effect does the not (!) operator have on high impedance and don't care conditions?
I'm writing some verilog and simulating it using modelsim. I have a block that looks like this:
...
0
votes
2answers
86 views
Digital bargraph display driver circuit
.For a project I need to display a progress bar of the activity performed by my MCU. For this purpose I am going to use a bargraph display, but the problem is that bargraph display driver driver ...
1
vote
0answers
140 views
Error-Detection Circuit — How does this work?
I'm currently studying for finals (I have the solutions here already, so this isn't helping me bypass doing homework or anything like that.)
My professor has done an unsatisfactory job explaining ...
2
votes
3answers
133 views
Help with designing a circuit with logic gates
I want to build a circuit with the following design:
3 inputs
1 NOT gate
2 AND gates
1 OR gate
This is my truth table:
...
0
votes
0answers
64 views
Using D-Flip Flop for MSB and JK-FF for LSB
I have the above question as an exercise. I know how to do all of the operations. However, I didn't get the point where it says "You are required to use a D-FF for the
MSB, (A) and a JK-FF for the ...
0
votes
1answer
91 views
Maximum and Minimum delay of combinational logic circuits
I am preparing for my exam and I am stuck with this past year question:
In the circuit shown below, the blocks A, B, C, and S are combination logic circuits. FF1 to FF3 are D flip-flops with same ...
-1
votes
1answer
133 views
Best FPGA to work with [closed]
I want to work on DSP and artificial intelligence for my freshman project, I was thinking on make an FPGA based system, the problem is that I have little experience working with FPGA's; I already know ...
0
votes
5answers
157 views
What does 0 and 1 mean in logic gate (NOT gate to be specific here)
When the input to a NOT gate is 1, the output is 0. When the input is 0, the output is 1.
Now, does the input being 0 mean that no current is flowing into the gate and then out of the gate towards ...
2
votes
1answer
71 views
Is a 40109 fit for 3V3 <=> 5V level shifting?
I have checked couple of datasheets for 40109 and although they specify "Supply Voltage Range" as min: 3V, max: 18V, none of the other tables specify values for < 5V.
Can I safely order these ...
0
votes
3answers
254 views
Why do we still take digital logic? [closed]
I am a student in Computer Engineering, and I am wondering why programs still teach digital logic. We have already taken a computer organization class in which we learn about computer architecture ...
6
votes
2answers
96 views
process timing on FPGA
I'm new to fpgas, and there are some timing subtleties that I'm not sure I understand: if all my synchronous processes are triggered on the same edge, then that means my inputs are 'captured' on one ...
-2
votes
1answer
44 views
what are the things to keep in mind when interfacing two digital devices?
what are the things to keep in mind when interfacing two digital devices, e.g FPGA with a dual shock controller or CPLD with a PS/2 Mouse, Microcontroller with an FPGA, FPGA with an external RAM.
One ...
-1
votes
1answer
80 views
what type of electronics job would combine mathematics, electronic design and programming into one [closed]
There are quite a few different areas of jobs in the Electronics industry.
We have Analogue, Digital, Embedded, Telecommunications, Control and much more. What I wish to know is that what job would ...
3
votes
4answers
102 views
ADC resolution selection
I want to convert analog output of an accelerometer to digital codes.
I understand that the sampling rate of the ADC should be with reference to Nyquist criteria.
Please let me know how to decide ...
2
votes
1answer
93 views
Reed switch stays ON
I have an anemometer reed switch connected to a uC with a 10K pull-up. I then have a RC filter to debounce around 500Hz. This is the case:
A fairly old anemometer connected to my board powers the ...
0
votes
2answers
66 views
Signal to Noise ratio problem
A 200mv peak to peak sinusoidal signal is applied to an ideal 12 bit A/D converter, for which Vref(v p-p full scale) is 5v. Find signal to noise ratio.
This is a problem worked out by one of my ...
