All Questions
13 questions
0
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DDRX Memory : What does DRAM prefetch mean? Also, why is the I/O bus clock half of the transfer rate?
While looking at the chart below, I had a question about DRAM prefetch & I/O Bus clock.
The characteristic of DDR is that it transfers 2 sets of data every cycle.
Therefore, for older versions of ...
- 1
2
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1
answer
722
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Why is the DDR termination voltage half the supply voltage? [closed]
Why is the DDR termination voltage (VTT) one-half the VDD voltage?
- 3,933
0
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0
answers
72
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How do I find out what pins of an Intel FPGA can be used to connect to different pin groups in EMIF?
If I want to connect my Intel FPGA using EMIF to a high speed DDR Memory e.g Cyclone IV E to DDR3 memory or Max 10 to DDR2 memory, how do I find out what pins can be used for the data, strobe, clock, ...
- 12.4k
-2
votes
1
answer
474
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Additive latency for DRAM READ and WRITE commands [closed]
In TN-47-10 – DDR2 Posted CAS# Additive Latency Technical Note , what does it exactly mean by Additive latency (AL = 1) is only used for READ commands and will not affect WRITE command timing ?
- 423
4
votes
1
answer
520
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Why do DDR RAMs have both xDQ and xDM signals?
DDR2 RAMs have these control signals
RAS, CAS - address strobes
UDQ, LDQ - byte strobes
WE - write enable
UDM, LDM - write mask
Why do we need UDM and LDM? Can't you write a byte by asserting WE and ...
3
votes
3
answers
824
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what is the most difficult part of creating a DDR2 or DDR3 memory controller inside an FPGA?
In this day and age we can just use the memory IP provided to us by the FPGA vendor be it a soft IP or hard IP. This makes it almost trivial to communicate with high speed memory devices like DDR2 and ...
- 2,337
2
votes
0
answers
450
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DDR2 and DDR3 ODT and ZQ calibration
Can anyone please explain what is the difference in ODT and ZQ technique used in DDR2 and DDR3??
Which method is very useful for DDR2 termination? whether ODT or External parallel termination??
...
- 117
2
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1
answer
744
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What is the more frequent error in DDR Memory?
this is about DDR memory data corruption and not about STUCK address or data lines. If we have a good DDR with no memory stuck issues and we perform lots of writes and reads which type of error is ...
- 43
5
votes
2
answers
1k
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waveforms showing effect of trace-length matching for SHORT ddr/ddr2/ddr3 traces?
I've seen lots of waveform plots that illustrate the beneficial effect of things like on-die termination, and the effect is unmistakable. For example, see page 6 of this Micron technical note. I'm ...
- 173
1
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2
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Series Termination DDR
I was Going through some application notes for the placement of Series termination of DDR and found it should be placed near to the processor.
But if I am not wrong termination resistor are placed to ...
- 1,514
9
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2
answers
7k
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Why are All DDRs' (DDR, DDR2, DDR3) Internal Clock Set to 200MHz?
If we see the DDR Upgrade technology explain below the internal clock of all DDR is set to 200 MHz.
DDR
For example,DDR-400
Efficient frequency data bus is 400 MHz
True clock rate (IO buffer ...
- 1,514
2
votes
1
answer
2k
views
What is DDR software leveling?
What is DDR software leveling ?
How it is different from DDR2 and DDR3 ?
Why it is required and important ?
Is there a hardware leveling ?
I have found some explanation here about DDR3 and a ...
- 131
9
votes
1
answer
2k
views
Is there a PCB-layout related reasoning behind DDR memory package and footprint?
BGA DDR packages have a unique footprint. There are two columns of pads on both sides of the device, and an empty column in between.
Is there a reasoning behind the placement of these pads (in terms ...
- 2,270