All Questions
40 questions
0
votes
1
answer
122
views
DDR with ARTIX 7 is not initialaizing
We are using Artix7 200T in our design.
We are using two independent DDR3L (MT41K512M16VRP-107 AAT) interface in our card.
Both with 8Gb capacity with 16 bit data width.
Both DDR is completely ...
user398283
0
votes
1
answer
292
views
Ferrite bead vs feed through capacitors for LPDDR4
I am designing a TI's AM6442 processor board
I am using SK-AM64x their development board as desgin reference.
There are two version an older and a newer
Old version schemtatic:
New version ...
- 529
6
votes
2
answers
407
views
LPDDR4 layout, should we avoid having signals in same byte group on different layers?
Is it a bad idea to route intra byte DQx on different layers?
I am trying to interface AM6442 to LPDDR4 16bit. I have followed every constraint in TI's DDR layout guidelines to the letter, ...
- 529
3
votes
3
answers
382
views
Is my meander a bad idea?
Autodesk Eagle's Meander:
My compact meander:
How bad of an idea is it to use "My compact meander" meander instead of the Eagles's version? The Autodesk Eagle's meander tool is very bad, ...
- 529
1
vote
1
answer
158
views
How are oscilloscopes able to fill DDR SDRAM memory without interruptions from memory refresh?
From the many teardown videos, it is clear that modern oscilloscopes mostly use DDR memory. But this memory needs to be refreshed periodically. Which should interrupt the data stream. I understand ...
- 33
0
votes
0
answers
110
views
DDR pin swaping why D0, D8, D16, D24, D32, D40, D48, and D56 are fixed
Below image is taken from Hardware Development Guide
for i.MX 6SoloLite
Applications Processors.
You can see that in each byte lane first and last bit are fixed.You are not allowed to swap.
May I know ...
- 3,933
0
votes
1
answer
2k
views
DDRX Memory : What does DRAM prefetch mean? Also, why is the I/O bus clock half of the transfer rate?
While looking at the chart below, I had a question about DRAM prefetch & I/O Bus clock.
The characteristic of DDR is that it transfers 2 sets of data every cycle.
Therefore, for older versions of ...
- 1
2
votes
1
answer
160
views
Why is there a tRRD in DDR3? There does not seem to be a resource conflict between different banks
In DDR3, bank activation is specific to the Bank, for different banks, they all have their own sense amp and do not seem to affect each other, so why would there be tRRD?
- 21
2
votes
1
answer
722
views
Why is the DDR termination voltage half the supply voltage? [closed]
Why is the DDR termination voltage (VTT) one-half the VDD voltage?
- 3,933
3
votes
1
answer
909
views
Why is the burst order of DDR3 DRAM not sequential?
Based on the JEDEC DDR3 documentation as shown below, when we are reading with burst length of 8 and starting column address of 010 (0x2), the burst order will be <...
- 1,094
1
vote
2
answers
4k
views
What is mean by VREF Training in DDR4?
While going through DDR3 and DDR4, there is a term called vref. Where in DDR3 it is outside the DDR and for DDR4 it is inside the chip. Why we need training for it. What is the use of it.
- 553
2
votes
1
answer
397
views
Length matching on DDR3 dataline in simulation for STM32MP1
I'm using HyperLynx to emulate my STM32MP157AAA3 small form factor system board with DDR3-1066 memory.
When I use DDRx batch simulation:
I confirmed that my ODT model is configured correctly. Use 48 ...
- 23
0
votes
0
answers
72
views
How do I find out what pins of an Intel FPGA can be used to connect to different pin groups in EMIF?
If I want to connect my Intel FPGA using EMIF to a high speed DDR Memory e.g Cyclone IV E to DDR3 memory or Max 10 to DDR2 memory, how do I find out what pins can be used for the data, strobe, clock, ...
- 12.4k
1
vote
0
answers
32
views
DDR interfacing with rockers3399 processor
I am using rockers 3399 processor in one of my applications. if you see page no 9 'External Memory or Storage device' section you can see the below things
*Support 2 channels, each channel is 16 or ...
- 3,933
-2
votes
1
answer
474
views
Additive latency for DRAM READ and WRITE commands [closed]
In TN-47-10 – DDR2 Posted CAS# Additive Latency Technical Note , what does it exactly mean by Additive latency (AL = 1) is only used for READ commands and will not affect WRITE command timing ?
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