All Questions
28 questions
2
votes
1
answer
124
views
How do I pass a clock signal through an FPGA while redriving it?
I would like to "pass through" a clock signal in an FPGA, while redriving it.
I would also like to calculate other signals synchronously with the clock and output them (to be sampled on ...
- 319
1
vote
2
answers
1k
views
What is the fastest achievable output speed for an FPGA?
To sum up the question, I would like to know what is the maximum frequency with which I can toggle an output of an FPGA. I do not intend this question to be specific to any particular board or vendor. ...
- 555
0
votes
2
answers
264
views
What are the options to interface Altera or Xilinx FPGA with a microprocessor or microcontroller?
I am trying to design a system which has some sensors connected to an FPGA and want to transfer the sensor data from the FPGA to a microprocessor like NXP IMX. I am new to FPGA and would like to know ...
- 87
2
votes
1
answer
160
views
Why is there a tRRD in DDR3? There does not seem to be a resource conflict between different banks
In DDR3, bank activation is specific to the Bank, for different banks, they all have their own sense amp and do not seem to affect each other, so why would there be tRRD?
- 21
0
votes
2
answers
302
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Is there any chance to embed two DDR IP cores into FPGA so that I can implement dual-channel memory architecture?
What I want is to implement a dual-channel memory architecture on a FPGA development board and verify that it is really faster than single channel.
At first I was thinking of configuring on-board DDR ...
- 21
0
votes
0
answers
161
views
How many DDR memory chips can be connected to Zynq UltraScale+ MPSoC ZCU104
I have a question regarding Zynq UltraScale+ MPSoC: how many DDR RAMs can be connected to the ZU7EV device, including both PS and PL banks ?
Here is the link for TRM.
- 1
-2
votes
1
answer
474
views
Additive latency for DRAM READ and WRITE commands [closed]
In TN-47-10 – DDR2 Posted CAS# Additive Latency Technical Note , what does it exactly mean by Additive latency (AL = 1) is only used for READ commands and will not affect WRITE command timing ?
- 423
0
votes
0
answers
136
views
Xilinx primitives for DDR3 memory controller
I have finished simulating a Micron DDR3 controller,
the DDR3 schematics and verilog code are located at https://github.com/promach/DDR
However, I have concern on implementing it on the Spartan-...
- 423
1
vote
1
answer
1k
views
tRAS definition for DDR memory
In Figure 3 of https://www.systemverilog.io/understanding-ddr4-timing-parameters#refresh , why tRAS is defined as the max timing between two REFRESH commands ? This ...
- 423
0
votes
0
answers
194
views
C code for DDR Access in Xilinx SoC devices
In my design, I want to write to DDR and then I want to fetch the data from DDR memory and then pass them to FPGA to be processed, after that, the data will be written back to DDR memory.I am using ...
3
votes
3
answers
824
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what is the most difficult part of creating a DDR2 or DDR3 memory controller inside an FPGA?
In this day and age we can just use the memory IP provided to us by the FPGA vendor be it a soft IP or hard IP. This makes it almost trivial to communicate with high speed memory devices like DDR2 and ...
- 2,337
1
vote
1
answer
532
views
There is a way to write into FIFO on both clock edges?
Im using Lattice ECP3 FPGA, didnt found any information about it on the internet.
I have ADC which providing me 12bits data on both clock edges, so I used Lattice High Speed I/O Interface:
This ...
- 559
0
votes
1
answer
1k
views
Lattice FPGA problems with built-in DELAY module
I'm trying to delay an input data coming from ADC component in DDR to my FPGA, afterwards output it in the clock rising edge.
The ADC Im using: ADS5463:
Im using Lattice ECP3 FPGA, based on the fpga ...
- 559
0
votes
2
answers
706
views
How to Output DDR data to 1 register
I have an Input which provides DDR data, I need to capture it and output it from the FPGA in one register (12bit).
How can I do it?
What I did for now is to capture the input data with always block ...
- 559
0
votes
0
answers
124
views
DDR3 RAM - possible Row Hammer
Tl; Dr;
I make a lot of reads to a RAM, physically incrementing the address and get more errors every time i restart the read process on address 0x0. Is this the Row-Hammer ?
I made a question ...
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