HDL (Hardware Description Language) is a description language used to describe the behavior of digital circuits. Examples are Verilog, VHDL and ABEL.
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High Level Language to HDL [closed]
I need to convert a simple program (C or Java) to HDL (especially Verilog). However, I have no idea about this conversion.
Another problem is that the resulting code must be gate level. Now, This ...
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42 views
How to design a fair Synchronous Arbiter?
The problem i am facing is this, i need a Hardware circuit which decides fair between for example bus requests which happen at the same time.
Example:
A and B are the two components which do memory ...
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1answer
63 views
How Verilog or VHDL projects are implement as physical chips?
In real life, how would I implement a circuit design using Verilog and VHDL as physical chip? Do I send the code to some third party so it manufactures the chip, like with PCB printing providers?
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Do I have to explicitly connect all pins of the ethernet chip in the FPGA when designing a new controller?
Regarding the Ethernet peripheral of the Spartan 3E FPGA specifically the SMSC LAN83C185 Ethernet chip. The task is to create our own interface between the PLB and the ethernet chip. So far, I've been ...
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117 views
Correct way to define propagation delays in VHDL
I'm currently learning VHDL. As an exercise I decided to implement some of the 7400 series chips. Below is the 74153 and while testing it with ghdl/gtkwave it seems to work.
But I'm sure this ...
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Any benefits from implementing CSA versus just using multiplication symbol when synthesizing?
I am synthesizing some multiplication units in Verilog and I was wondering if you generally get better results in terms of area/power savings if you implement your own CSA using Booth Encoding when ...
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248 views
Logic design for FPGAs using C
I am well aware about programming processors and microcontrollers in C. But can C code (not SystemC) be used for logic design for FPGAs? Are there any specific software tools for this purpose?
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94 views
Curious state transitions in state machine RTL simulation
I have a simple state machine as part of my Verilog module:
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60 views
Verilog - Weird blocking/nonblocking problem
In the rst block in the following code I get a strange error whenever I use non-blocking assignment/ The State_SENDSYNC last for two cycles even though it's supposed to only last one cycle. Changing ...
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154 views
How to use HDL designs in hobby circuits and how to do transistor level tuning [closed]
Please excuse the noobness.
What is the process a lone (or few) individual can send an HDL design off to a fab (tools, file formats, potential fabs)? I have played around with FPGAs but I'm curious ...
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1answer
56 views
Grouping input and output signals with the corresponding clock
In my Verilog design, I have two asynchronous clocks, clk1 and clk2. Associated with each clock is a bunch of inputs and ...
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3answers
104 views
Timings constrains for isochronous clocks
In my Verilog design, I have two clocks of the same frequency, but of different phase. At the moment, my timing constraints look like this:
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2answers
507 views
RTL vs HDL? Whats the difference
What is the main difference between RTL and HDL? To be honest I searched / googled it yet people are divided in their opinions. I remember one saying that HDL is the computer language used to describe ...
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80 views
Adjustable clock in HDL
I need to generate an adjustable clock in hdl (verilog) on altera cyclone II fpga using signal probes (blocks that can change their output value through jtag - there is no need to recompile the code). ...
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125 views
3-phase lock loop in verilog
I want to implement a phase lock loop in verilog hdl. The input is the source voltage (which is a sine wave) and the output is theta(in terms of sin and cos).
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317 views
Mismatch between RTL-level simulation and post-synthesis simulation using xilinx xst
I have written a verilog code and RTL simulation is working fine. After this I synthesized the design using XST tool in Xilinx ISE 13.2. The post-synthesis simulation is showing some unexpected ...
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114 views
HDL Designer: What's the difference between a project and a library?
Which should I use? I'd like to use it to model circuits for homework and to possibly reuse parts circuits in other designs.
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3answers
287 views
Difference between RTL and Behavioral verilog
Can someone tell me what is the difference between RTL and behavioral Verilog code? Is there any clear cut demarcation between designs at these two levels?
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1answer
108 views
Processor - L1 Data cache interface
Sorry if the following looks like a very specialized (or programming) question, but I'm hoping there are people on this forum who have done VHDL/Verilog modeling, and might be able to answer:
I'm ...
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3answers
162 views
VHDL Error (Simple Expression Expected)
I'm new to VHDL and I'm having a problem with my code that I can't seem to fix. We're supposed to do this using either selected signal assignment or table lookup. Mine is kind of a combination of the ...
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4answers
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simulating fpga design without having the actual hardware
Im new to fpga and currently taking HDL (Verilog particularly) class. I have sufficient knowledge in digital design like combinational and sequential circuits.
I want to create a project similar to ...
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2answers
240 views
Developing hardware in FPGA with LED Driver Chip
I asked related TI TLC5944 LED Driver questions here, here and here
Actually initially I was supposed to simulate the following design. I had to simulate the driver functionality also (as the driver ...
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4answers
191 views
In which cases should I use Z as output in HDL?
I created a simple multiplexer which feeds different input into output depending on statemachine.
Now there are states when I do not need the output so I usually set it to 0.
...
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279 views
What is backdoor memory access?
There is a term in HDL simulation/verification called
"backdoor memory access".
I've heard this a lot of times though I'm
not sure how is this implemented.
Also, there are a few references for this ...
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147 views
Simulating IBIS Model in modelSim
I am developing a logic in an FPGA that will act as a controller for a chip by TI. I got the TI chip IBIS model from the TI website.
My controller is ready and I want to simulate it using ModelSim. ...
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2answers
138 views
Automating test vector in Verilog HDL
This is my first attempt at learning Verilog HDL testbench for an AND gate:
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1answer
53 views
What is the best way to understand a large existing HDL core?
Groundhog is a open source SATA host bus adapter core written in Verilog. I was wondering if anyone had tips on how to begin to understand how it operates? Is it to go from the high-level to ...
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190 views
Developing for an FPGA using Impulse C
I am considering using Impulse C to write C code that will compile down to HDL for my FPGA. I'm curious as to what experiences people have had with Impulse C, to better understand the advantages and ...
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What is a false path timing constraint?
In FPGA world, what exactly are false path constraints for an HDL compiler? Why are they useful?
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Why are inferred latches bad?
My compiler complains about inferred latches in my combinatorial loops (always @(*), in Verilog). I was also told that inferred latches should preferably be ...
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231 views
Where is the software / hardware boundary in modern computer systems?
Computers are pogrammed in (and controlled by) software. That software is often run by other software (e.g. Java compiled into bytecode, run by a Java VM coded in machine instructions), which is in ...
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994 views
What happens when an FPGA is “programmed”?
From what I understand, the process of programming an FPGA comes in two parts:
Encode the hardware description into bits that the FPGA can understand (i.e. write some HDL and compile it)
Load the ...
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2answers
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Verilog: Check for two negedges in always block
i try to do something like this:
always @ (negedge speed_dec or negedge speed_inc)
begin
do something
end
This doesn't work as checking for 2 negative edges ...
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2answers
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How to assign value to bidirectional port in verilog?
I'm trying to use a bidirectional port in Verilog so I can send a receive data through it. My problem is that when I try to assign a value to the port inside a task, but I keep getting an error.
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What was the motivation for making behavioral descriptions such a big part of Verilog?
I don't use Verilog for anything serious, but I use it in my classes, and I'm starting to think I must be missing something about the appeal of behavioral hardware description.
When I write Verilog I ...
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VHDL or Verilog?
VHDL and Verilog are the HDLs of the day. What are the advantages of either for someone who has no experience with HDLs at all?
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recommandation webpage/book to learn asmd chart over using verilog
I have searched so many website to take background about how asm chart is used in verilog code.However, I could not find any web cite with sufficient examples to learn asm chart. Can anyone give or ...
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518 views
Is there a free/low-cost bus monitor in VHDL/Verilog for ARM AXI/AXI4 and/or AXI4-Stream protocols?
I am looking for something to log the read and writes on an AXI 4 bus to a file. And similar for AXI4-Stream. For what it is worth, this is for Xilinx. I could roll my own, but I hoped someone else ...
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315 views
How does Xilinx ISE determine compilation order?
I’m working on a VHDL project which is a small SDRAM test. I have these entities:
top
sdramwrapper
sdram <– generated IP core sdrampkg <– contains a package containing constants used several ...
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how to write output of the monitor to a file
I have a testbench and a verilog modules. I want to write ouput of the testbench to a file anmed as output.txt. While doing this job, I want to use $monitor.
Is it possible ? If yes, can you give me ...
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What language is Cadence's Emanger *.ecom files written in?
I know this is a long shot but I thought I would ask while I am waiting for the FAE to get back to me. This is related to Cadence Verilog simulations and regressions.
I am trying to debug an *.ecom ...
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270 views
System Generator: How to make a channel selector?
I want a system with two inputs,sel and in, and at least two outputs channel A and ...
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2answers
326 views
Is there a free cross-platform tool for pure digital gate-level schematic design and simulation?
I'm searching a software tool for teaching purpose in order to teach students digital hardware (starting from logic gates level).
Do you have something in mind that will allow making simple graphical ...
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7answers
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How much does it cost to have a custom ASIC made?
I have browsed several ASIC manufacturer's webs, but I haven't found an actual number.
I assume there would be a fixed cost associated with creating masks and such and then there will be a cost per ...
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4answers
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Exercise based book to learn Verilog/vhdl?
I was planning on learn an HDL (preferably verilog as I have to take a course in it in subsequent semesters). My initial plan was to first learn the syntax and then implement all the digital systems I ...
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How do I learn HDL
I have a course in Digital Design in this semester and just love it. Now I know that most of the work in embedded system and digital design is done on computer simulators first and then implemented ...
