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I made the following program for displaying no of days in the user provided month. And to check whether the year user entered is leap year or not. I am trying to make the program on data flow level. I don't know whether I can use if/else in data flow level in Verilog. The following program is giving me errors at the notified place.

module LeapYear(year,month,leapOrNot,Days);

input year,month;

output leapOrNot,Days;
 // error here
      if((year&400)==0) && ((year % 100)!==0 || (year & 4)==0)begin
       leapOrNot=1;
       end
  else

if(month==4 || month==6|| month==9|| month==11)begin
    Days=30;
end else
    if(month==1 || month==3|| month==5|| month==7|| month==8|| month==10|| month==12)begin
         Days=31;
  end  else
        if(month==2 && leapOrNot==1) begin
            Days=29;
     end   else begin
              Days=28;
              end

  endmodule

Please tell me what is the reason for this error. There error is 

 ** Error: C:/Modeltech_5.7f/examples/LeapYear.v(9): near "if": syntax error

Regards

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Are we supposed to guess what the error message is? – Dave Tweed Dec 18 '12 at 16:43
I am updated the question. And please tell me if it is allowed to use if/else in data flow level programming – Alfred Dec 18 '12 at 16:50

2 Answers

up vote 1 down vote

You have 

    if((year&400)==0) && ((year % 100)!==0 || (year & 4)==0) begin
//    ^             ^
       leapOrNot=1;
     end

The two parenthesis that I marked in the code are matching each other, making the tool think this is the complete condition for the if statement. The tool expects the begin to be immediately after the close-parenthesis.

According to The Verilog Golden Reference Guide, it's required to put a parenthesis around the whole conditional expression in the if statement.

    if (((year&400)==0) && ((year % 100)!==0 || (year & 4)==0)) begin
//     ^                                                      ^
//     Added                                                  Added
       leapOrNot=1;
    end
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up vote 3 down vote

Your code has many, many problems. Balancing parentheses is among the least of them.

First of all, an if statement can only appear in the body of a behavioral (always) statement/block. This is the cause of the error message you listed.

Secondly, module input ports can't be integers, which is what you seem to be assuming. Multi-bit values need to be given explicit widths.

There are also many other syntax, logic and style issues, too numerous to get into. Try the following code instead.

module LeapYear (year, month, leapOrNot, Days);

input [15:0] year;    // 0-65535
input  [3:0] month;   // 1-12

output leapOrNot;
reg    leapOrNot;

output Days;
reg    Days;

always @* begin
  if ((year % 400) == 0 && (year % 100) != 0 && (year % 4) == 0) begin
    leapOrNot <= 1;
  end else begin
    leapOrNot <= 0;
  end
end

always @* begin
  if (month==2) begin
    if (leapOrNot==1) begin
      Days <= 29;
    end else begin
      Days <= 28;
    end
  end else if (month==4 || month==6 || month==9 || month==11) begin
    Days <= 30;
  end else begin
    Days <= 31;
  end
end

endmodule
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