Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.
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Clocked edge-triggered timing (contamination delay)
I'm reading a book about computer architecture, and it says that, in clocked edge-triggered devices, the contamination delay is usually nonzero, and that the contamination delay for registers is ...
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1answer
46 views
Choosing Altera Quartus II clock rate for stopper
I'm using Altera Quartus II to built a stopper. I'm using 2 counters and I need to choose the right clock rate to get pulse every 1 sec. There are only two options in Quartus for the clock: 27Mhz and ...
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1answer
52 views
Why do we need the MOESI/MESIF protocols?
As I understand, those two protocols add an extra state to identify which cache should respond to a miss request from another cache for a particular cache-line.
But, in the MESI protocol, only one ...
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0answers
33 views
Is my interpretation of this problem regarding a 7-word mux correct?
I have a problem on an assignment which states to draw a block diagram for a 7-word MUX and determine how many control switches it should have. I'm not exactly sure what the problem means by "7-Word." ...
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39 views
Virtual Memory, Cache, and TLB's
I recently asked this question over at stackoverflow, but I was told by a user that it was off-topic, so I am posting it here since it's more of a hardware question.
I'm trying to study for an exam ...
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1answer
97 views
Building a simple PC - looking for a CPU [closed]
I would like to build a computer. It is a child's dream that I had and now that I am at college, I finally gain the knowledge I need.
I want it to be simple. I admire the early designs of 1990's ...
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2answers
96 views
Programming microcontrollers in ASM or C & how it's done
Just to clarify on these topics:
If I were to program a microcontroller in ASM I would use an assembler, of course. The assembler would compile the code into opcodes (machine code?)(generally 1:1 ...
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1answer
81 views
What software to graphically design a simple schematic? [duplicate]
I need to draw a schematic similar to that shown in the figure attached in this question.
Are there softwares that allow to graphically design a schematic like that?
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33 views
Memory technology survey?
I did a comparison on what I could find about access times for different memory systems, could you please say if these numbers are approimately correct (I use an Altera DE2 FPGA)?
SDRAM: Slower that ...
0
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1answer
126 views
What does “CL” stand for in this processor architecture block diagram?
I'm learning about pipelining but can't understand this abbreviation: "CL". You can see it in processors' schemes.
It is shown with with and without a line above it; what is the line for?
Diagram ...
4
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3answers
202 views
How can the number of clock cycles required to complete an instruction in a pipelined processor less than pipeline latency?
I am not new to computer architecture but I have only academic experience with micro-architecture implementation.
I have heard and read this many times but never really bothered to understand the ...
2
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1answer
76 views
Memory Organization in Computer
How is memory stored in a computer? Is it 1 bit per address so in order to get the value of an integer (32 bits) it must go through 32 addresses, get all the bits of 0's and 1's? I am a bit confused ...
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0answers
130 views
How does a computer work? [closed]
I am a software programmer.I am very much curious to know about the behind the scenes of how actually a computer works.
By HOW I mean:On the hardware level.
My knowledge about software programming ...
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1answer
148 views
How many bits are used for the tag, block, and offset fields for the representation of a memory address?
A small byte-addressable embedded computer system, with a word length
of 32 bits, has a main memory consisting of 4 KBytes. It also has a
small data cache capable of holding eight 32-bit words, ...
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1answer
139 views
What are ALMs, LEs and ALUTs?
Does ALM mean "Adaptive logic module"?
www.altera.com/literature/ds/ds_nios2_perf.pdf
Jul 1, 2013 -
One ALUT is equivalent to about 1.25 LEs.
Does LE mean logic element and ALUT means ...
2
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1answer
212 views
How to wire a system for Nios 2 in Qsys?
I've managed to reduce the number of errors but I still have some:
...
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79 views
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3answers
75 views
How is 'specific' data found and taken from a Semiconductor Memory Source?
In a semiconductor memory chip, each bit of binary data is stored in a tiny circuit called a memory cell consisting of one to several transistors. Volatile type.
Suppose an application stored its ...
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4answers
303 views
Do computers speed up at higher temperatures?
At higher temperatures, will computers get faster? Evidently, one always wants cool a computer down as higher temperatures can damage core components.
However, is it an interplay between silicon, ...
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0answers
160 views
SAP-1 (Simple as Possible) W Bus
I'm currently investigating the SAP-1 to build in order to grasp a really good understanding of simple 8 bit computers.
There are a few questions that I would like clearing up.
What exactly is the ...
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3answers
217 views
Is it true that copying is the most CPU intensive operation?
A mech engineer said that copying puts more load on the microprocessor than "other" operations (e.g. moving data or creating the same amount of new data). Is this true? Can you elaborate? I understand ...
0
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1answer
66 views
Ratio between register and primary memory access?
I've been doing research to find how much faster register access is compared to primary memory. I find the ration is about 100 times faster, can that be correct, has it always been about that number ...
0
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0answers
47 views
MIC1 Architecture High bit Circuit
Does anyone know what the MIC1 High bit circuit looks like? Or at least the truth table so that I can construct it and get an understanding of it.
Here is a picture of the Architecture. The high bit ...
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2answers
383 views
Differences, uses, and theory of volatile and nonvolatile memory?
I understand the basics of volatile and nonvolatile memory. Volatile memory requires a constant power supply to retain data whereas non-volatile memory does not require a constant power supply to ...
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2answers
142 views
Is the registry file made from SRAM?
I study computer engineering and I read Hennessy's book about Computer Organization where it's described how the microprocessor does pipelining and that the microproceossor has on-chip cache, as much ...
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1answer
105 views
Does anyone know the hardware of a Nike+ SportWatch GPS?
I have one of these devices and I would really love to figure out if it is possible to write and push my own firmware into the device. The software on the watch is pretty limited and I would like to ...
0
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1answer
54 views
unable to understand write policy in Cache memory
I am studying write policies in cache memory ( for first time ). I am able to understand the 'write-through' but i am not able to understand 'write back' and the problems associated with it . Please ...
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2answers
295 views
Instruction Register? Whats it's purpose/how is it connected? (And what happens after)
So im learning the SAP 1 Computer Architecture. Most things I get pretty well, but from what I understand: (Lets pretend it's an 8bit and address is 4 bits and opcode is 4bit)
...
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2answers
184 views
Classic RISC pipeline question
Consider the following instruction sequence:
Add R3, R4, R5 (R4+R5->R3)
Or R2, R4, R5 (R4 OR R5->R2)
Add R1, R2, R3 (R2+R3->R1)
Assuming no data ...
0
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1answer
76 views
What's the difference between delayed branch and branch prediction?
I'm studying how delayed branch works and I'm trying to distinguish delayed branch from branch prediction. What is the difference? Is delayed branch a means to facilitate a control hazard?
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1answer
41 views
How to calculate the address fields for a cache?
I've a homework question about 32-bit cache memories:
For a cache memory that has size 16kB (16384 byte) and blocksize 2
words, state the names and the sizes of each field of the address that
...
1
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2answers
109 views
What is the meaning of “Register.Rd”?
Reading Hennesy's book "Computer Organization and Design" it is mentioned "Register.Rd" and "Register.Rs" but what does it mean? The .Rd, .Rt and .Rs parts I can't understand, on page 365:
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1answer
96 views
How is sign extension used in practice?
In wikipedia it says what sign extension is but it doesn't say what it's used for or when it is used. I read Hennesy's book "Computer Organization and Design" and it has a sign-extension mechanism ...
2
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1answer
122 views
What does RWM mean?
I'm studying computer hardware and the acronym "RWM" appears, so I wonder what it means? It has to do with LOADs and STOREs of instructions.
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1answer
618 views
How does the Store Word(SW) and Load Word(LW) instructions work, MIPS
The SW and LW instructions are defined as:
...
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1answer
133 views
Seeing how Instructions get Translated (Computer Architecture) [closed]
Little bit of a confusing question, also an x-post (Since it may be more suited here than SO). But anyways Im really looking for learning some low level programming. Thing is, Dev boards like ...
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2answers
100 views
What is the reason of RAM modules conflicts in terms of computer architecture?
What is the reason of such conflicts?
I read a book "Computer architecture" by Andrew Tanenbaum, but didn't understand the reasons may cause conflicts with memory with different timings, frequencies.
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1answer
65 views
How to best understand cache associativity?
AFAIK this definition is the most clear and physical:
Associativity number = Number of comparators.
Is it correct? Could you make a more precise / better definition?
The wikipedia illustration is ...
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1answer
117 views
Writing a method using MIPS code
I am trying to understand how convert C code to MIPS code and I have having trouble understanding why the stack pointer( $sp ) needs to be manipulated before and after the procedural code.Isn't the ...
3
votes
1answer
432 views
How can a CPU dynamically change its clock frequency?
My Intel CPU changes clock speed depending on the usage, but how does it decide what clock speed to run at? Is the clock speed determined by the OS software using an algorithm, or is it hardware ...
7
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3answers
259 views
What does it mean for a CPU to support a stack?
How can a CPU not support a stack? Doesn't any architecture that uses subroutines (I'm pretty sure that's all architectures) have to push the return address onto the stack so it can return to where it ...
23
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6answers
1k views
Why is open hardware so rare? [closed]
I'm trying to understand why open hardware is so much harder to come by than software. I've tried looking around online and I couldn't find as satisfactory explanation.
I understand that hardware is ...
2
votes
1answer
108 views
Processor - L1 Data cache interface
Sorry if the following looks like a very specialized (or programming) question, but I'm hoping there are people on this forum who have done VHDL/Verilog modeling, and might be able to answer:
I'm ...
11
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3answers
562 views
How does the Harvard architecture help?
I was reading about arduino and the AVR architecture and got stuck at the point that how does pipeline stall or bubbling is solved by Harvard architecture introduction in the AVR.I mean what Harvard ...
2
votes
1answer
196 views
Electrical Engineering vs Computer Engineering? [closed]
I am trying to decide whether to major in EE or CE. To my knowledge, computer engineering has the same core focus as electrical engineering but with an emphasis on digital logic and microprocessors. ...
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1answer
857 views
Using CCM (Core Coupled Memory) in STM32F4xx
STM32F4xx microcontrollers have 128KB of SRAM + 64KB of CCM SRAM. CMM SRAM is hardwired to data bus so it is impossible to use it with DMA.
What is the reason to add additional SRAM as CCM?
Does it ...
2
votes
1answer
304 views
How to calculate index and tag fields lengths for a cpu cache?
I study computer engeering notes for a cache memory and I try to understand what determines the length of the index and the tag fields. The first examples is for 64 bits and the second example is for ...
3
votes
1answer
486 views
What is CLK in UART/USART used for?
I'm studying computer architecture at my university and I've been recently asked a question: what is CLK used for in UART/USART? The first obvious thing is that it is used for dividing frequency when ...
2
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2answers
236 views
Verilog asynchronous reads of regs - and design question
I'm trying to understand what the following bit of behavioral code, what kind of hardware it turns into:
...
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2answers
226 views
What determines the number of bits for the address field in a cache memory?
I understand a cache memory is constructed for a basic block like this
Valid bit | Address bits | Data/Instruction
But what determines the length of the address bits? I understand that for a 32-bit ...
