Newest &#39;fpga&#39; Questions

-3

votes

0answers

34 views

Magnetic Levitation system control using Altera FPGA [on hold]

I want to design a controller to suspend a magnetic levitation ball in air using FPGA,I have some matlab simulations deals with my design and bringing the levitated ball to its desired position from ...

asked 11 hours ago

Rawaz
11

5

votes

1answer

68 views

FPGA output pin high capacity load

I am writing an interface for a HITACHI SX19V001-ZZA that is a color LCD display. Please have a look at the datasheet (pages 13-14) to understand the references I am going to make. My interface sadly ...

fpga

asked Feb 22 at 10:01

Vladimir Cravero
55519

1

vote

1answer

43 views

How the delay locked loop (DLL) align the clock?

The delay locked loop is used for align the clock in integrated circuits. In the IC there are no of flip flops and other devices. I want to know that how the DLL align the no of clocks going to ...

fpga pll clock-speed vlsi dll

asked Feb 21 at 6:28

user3244121
61

0

votes

2answers

69 views

Spartan 3AN (XC3S50AN) memory [closed]

Presently we are doing some automation operation using microcontrollers but I wish to change the technology to CPLD/FPGA. So, I wrote a Verilog program in XILINX (XC9572XL) but it has 72 micro-cells ...

fpga xilinx spartan

asked Feb 20 at 5:10

lokeshwaran kittappan
62

-1

votes

0answers

52 views

what happens when you remove your fpga from the power supply [closed]

What happens when you have been working with an FPGA (programmed a design, ran some tests, etc..), and then once your test is done, you remove the FGPA from your testing board without first turning ...

power-supply fpga

asked Feb 19 at 19:58

ps_chou
1

0

votes

1answer

47 views

Writing and Reading From FLASH ROM on Nexys 2 Spartan 3-E FPGA

I am a newbie to VHDL and FPGA platform. I have a Nexys-2 Spartan 3E FPGA board which is provided with a 16 MB Flash ROM.I want to preload first 10-20 memory locations of this ROM,each location with ...

fpga vhdl memory flash rom

asked Feb 17 at 14:52

user123
1

3

votes

4answers

180 views

What are the advantages to a separate processor when there is an FPGA present?

Consider an embedded application with both a discrete processor(ARM, AVR, PIC, etc) and an FPGA to offload some of the work or interface with specific hardware. Assuming there are sufficient ...

fpga microprocessor softcore

asked Feb 16 at 23:11

user1547129
161

3

votes

0answers

66 views

FPGA link to external memory

I am trying to use the cellular ram on the Nexys 4 FPGA development board. I am using Xilinx Vivado and would like a Microblaze soft core processor to be able to perform reads and writes. So far I ...

fpga memory ram controller

asked Feb 11 at 11:14

Marmstrong
161

2

votes

2answers

81 views

Using BRAM instead of SRAM in Virtex-5 FPGA

I am working on a project where we are capturing signals from an ADC using a Virtex-5 FPGA and the samples are being stored on a 128K x 256 SRAM from where the data samples are acquired by a PC. I ...

fpga xilinx sram

asked Feb 10 at 18:57

GamingX
433

2

votes

2answers

67 views

Using the PS/2 port of the Papilio One FPGA from VHDL

I'm trying to receive data from a keyboard via the PS/2 port on the Papilio One Arcade Megawing. Eventually I'll want to implement this from scratch, but I thought I'd get some public code working ...

fpga vhdl xilinx ps2

asked Feb 10 at 7:10

Cactus
1565

1

vote

3answers

76 views

fpga internal metastability

I have an issue which I think maybe related to internal timing issues. I know that crossing clock domains can cause metastability, because setup and hold timing not being kept. But I was thinking ...

fpga vhdl

asked Feb 7 at 15:27

JakobJ
669311

1

vote

1answer

40 views

Problem using FSL with microblaze

I want to pass some data from my verilog to my microblaze core in ISE 14.7. I was doing some research and it seemed like the FSL was the easiest way to go about this. What I did was create a ...

fpga xilinx microblaze

asked Feb 7 at 14:29

toozie21
61

1

vote

1answer

122 views

How is machine code handled by the microprocessor? [closed]

And no I don't mean "How do you write a program for a processor". What I want to know is how does a processor interpret some aribtrary instruction, say 100001 as ...

fpga microprocessor hdl

asked Feb 4 at 23:56

Igglyboo
112

0

votes

2answers

91 views

FPGA Input Signal measurement

How to measure input pulse signal's frequency using xilinx toolkit on matlab? Since I'm bad at coding,I use System generator on matlab. I'm doing a project, In which I'll be using a Proximity sensor ...

fpga counter spartan xilinx-system-generator

asked Feb 4 at 16:11

user36650
1

2

votes

1answer

56 views

Xilinx FPGA Input data timing constraint

I'm using Xilinx Spartan 6 Automotive FPGA. My FPGA design has a SPI interface to a external peripheral. From FPGA to the peripheral, I have these SPI related signals: spi clk spi data (mosi) - ...

fpga xilinx timing-analysis

asked Feb 3 at 8:10

wildwildwilliam
183

-1

votes

0answers

46 views

Usb Echo Verilog Module on Basys 2 FPGA

I want to create a module on my basys 2 fpga board which gives back a data coming from usb port as echo. It looks simple but I could not found anything useful so far. I just do not know how to read ...

usb fpga verilog data

asked Jan 28 at 20:13

Eray Tuncer
1

2

votes

2answers

68 views

cross clock domain databus

I asked a question some time ago about crossing clock domains Design practice crossing clock domains and async signals. One of the "rules" is to never synchronize multi-bit signal bit-by-bit, ...

fpga vhdl

asked Jan 27 at 14:38

JakobJ
669311

1

vote

1answer

49 views

Internal fmax of FPGA program

When I compile my project in QUARTUS, it provides me with information about "internal fmax" ...

fpga altera quartus-ii

asked Jan 27 at 2:21

Juribiyan
133

0

votes

3answers

157 views

Clock divider VHDL

I created a clock divider with the code below. i followed steps in prof chu's book. ...

fpga vhdl clock

asked Jan 22 at 15:41

Chanuka Perera
153

13

votes

8answers

1k views

When can FPGA's be used and Microcontrollers/DSPs not?

I have to choose between a course on advanced microcontrollers, and a course on advanced FPGA's. I have had introductory courses in both subjects, and what troubles me now is that I am already ...

microcontroller fpga dsp

asked Jan 22 at 13:41

Jolle
664

0

votes

1answer

58 views

Installing Microsemi/Actel Libero on Ubuntu [closed]

I am trying to install the latest version of the Libero SW tools set from Microsemi/Actel on my Ubuntu laptop. The web site of the company says that their SW only supports the RH linux and they don't ...

fpga cad install script

asked Jan 18 at 21:31

FarhadA
763111

0

votes

1answer

42 views

What is the use of OFFSET IN/OUT constraint for FPGA design when using register in IOB?

The following is asked in the context of Xilinx FPGAs (my experience), but may also apply to similar technologies offered by other vendors. Background: When writing constraints for FPGA I/O, there ...

fpga xilinx constraints

asked Jan 16 at 17:10

Josh
24625

1

vote

2answers

89 views

How to predict the memory size and gate count given source code

Excuse my poor English :-) I am in a software (for face detection) team and we co-work with the hardware team. If we give the source code to the hardware team, they will try to implement it with ...

fpga memory hardware

asked Jan 14 at 13:36

IKS
133

2

votes

1answer

86 views

Designing a peripheral for soft core CPU

I've been implementing a hardware module in VHDL for part of my university dissertation and I want to implement it as part of a NIOS II core in my cyclone 2 FPGA. This uses the Avalon interface, what ...

fpga altera chip-design softcore

asked Jan 12 at 21:56

Dean
3,56312066

2

votes

3answers

114 views

Design practice crossing clock domains and async signals

I have been designing a few projects on different FPGA's in VHDL, and it seems my most common source of "hard to find errors" is when I forget to synchronize an async signal, or forgets to resync a ...

fpga vhdl clock

asked Jan 11 at 18:14

JakobJ
669311

1

vote

1answer

50 views

fgpa timing constraint on enable signal

I have a question regarding setting timing constraints on enable signals. In my vhdl design I use an enable signal, to gate when the process needs to sample my input data. The enable signal is ...

fpga

asked Jan 10 at 10:37

JakobJ
669311

1

vote

2answers

164 views

Max switching frequency of GPIO pins of modern cheap FPGA

How can we estimate maximum switching frequency of GPIO FPGA pins? What is maximum data rate achievable when connecting two FPGAs together without using of integrated high-speed transceivers? Or when ...

fpga gpio high-speed bit-bang

asked Jan 1 at 21:11

osgx
360112

1

vote

1answer

101 views

Online FPGA/HDL synthesizer

I recall seeing a web-based HDL synthesizer a couple years ago, but I can't find it anymore. I believe it was just a frontend that ran the vendors' synthesis tools on the server. Does this sound ...

fpga verilog vhdl xilinx

asked Dec 26 '13 at 5:54

Rainbow
82

0

votes

0answers

41 views

ppc405 communication with custom ip ml403

I am trying to simulate a chemical reaction in FPGA. My basic FPGA architecure consists of 3 processes: ...

fpga c vhdl xilinx

asked Dec 19 '13 at 21:35

Jasim Khan Afridi
1

1

vote

0answers

58 views

Averlogic fifo experience?

I've got an fpga board that utilizes an averlogic fifo -- AL460. This should be the easiest part in the world to use -- it's basically a huge dual ported fifo with two independent clocks. I was ...

fpga memory fifo

asked Dec 18 '13 at 3:50

Doov
4197

8

votes

3answers

166 views

How to identify areas of a FPGA design that use the most resources and area?

I am working on a large FPGA design, and I am very close to the resource limits of the FPGA that I am currently using, the Xilinx LX16 in the CSG225 package. The design is also almost complete, ...

fpga vhdl xilinx spartan optimization

asked Dec 17 '13 at 6:19

Marcus10110
1364

0

votes

1answer

34 views

Why would my Lattice IceStick stop working when configuring the PLL?

I'm using a Lattice FGPA IceStick with the newer IceCube2 programming environment and the Diamond 3.0 programming tool. The 'iCEstick LED Rotation' example runs OK but when I attempt to enable the ...

fpga

asked Dec 16 '13 at 20:21

JimFred
1609

2

votes

0answers

85 views

Cyclone V FPGA SocKit - trying to use LCD from FPGA

I'm trying to use the LCD screen on a SocKit board with a Cyclone V FPGA. However, in the documentation I see that the chip is divided into an HPS and the FPGA and the LCD seems to be connected only ...

fpga spi vhdl altera cyclone

asked Dec 14 '13 at 23:00

MA81
111

2

votes

2answers

272 views

How to route a LVDS clock from FPGA input to output?

Using VHDL, How is it possible to receive a pair of LVDS signals (say external clock) on the FPGA and route them to another pairs of pins to go out, without any modification? I have tried IBUFDS and ...

fpga vhdl clock lvds

asked Dec 11 '13 at 20:20

dahma
414

1

vote

1answer

77 views

How to map LPC FMC pins to FPGA pins on a Zedboard? [closed]

How to map fpga pins to actual physical pins on the FMC connector on a Zedboard? Of course I have looked into the user's hardware guide and the master constraint file, but all I have found is a list ...

fpga xilinx

asked Dec 7 '13 at 12:23

dahma
414

4

votes

1answer

111 views

Is it possible for an FPGA to “partially” configure?

I have a spartan 6 board that I designed and am having some configuration issues. I'm using SPI flash to program the fpga (e.g. I use jtag to write the flash and the flash then writes the fpga). The ...

fpga xilinx configuration

asked Dec 6 '13 at 5:36

Doov
4197

1

vote

1answer

67 views

PCIE reference clock

I recently completed a PCI-E Gen 1.0 line card design. The line card consisted of 4 Spartan 6 FPGAs sharing one PCIE reference clock. Early on in the design there was a decision to solely use the PCIE ...

fpga ethernet clock pcie

asked Dec 4 '13 at 1:04

user2367353
61

1

vote

2answers

197 views

FPGA with low pin count (and therefore smaller and hopefully cheaper)

Are there any FPGAs with a low pin-count (8 to 16) and small package and hopefully cheap (nearly as cheap as a micro)? It seems that FPGAs are typically intended for massively parallel & fast ...

fpga

asked Dec 3 '13 at 17:35

JimFred
1609

2

votes

1answer

52 views

Constraining the reset line

I am using Quartus II to compile my Verilog design, and I'm working to properly constrain my signals. I know how to constrain clocks, for example: ...

fpga verilog quartus-ii timing-analysis

asked Dec 2 '13 at 11:03

Randomblue
3,05711359

2

votes

3answers

75 views

How to write to block memory?

I need to write 16x16 bit data to block memory. I am using RS232 to send data. To get 16 bit data, I send 2x8bit. Now, how can I write my data to the memory? I have a write signal and 16 bit input ...

fpga serial memory rs232

asked Nov 29 '13 at 20:41

g3d
1377

2

votes

3answers

159 views

Setting FPGA pins as virtual

I have a Verilog module for which I want to check its timing in isolation to the rest of the system. The problem is that the FPGA has a limited number of physical pins, and my module has more inputs ...

fpga verilog quartus-ii timing-analysis

asked Nov 29 '13 at 11:42

Randomblue
3,05711359

2

votes

4answers

153 views

Custom FPGA PCB with external programming circuit

My team has verified our logic design on a development board and we are ready to move to a final prototype. Due to the nature of the device, the FPGA board must contain minimal components and be ...

pcb fpga altera prototyping

asked Nov 27 '13 at 20:59

technocratic
132

1

vote

2answers

150 views

Project suggestions for Final Year [closed]

I'm a final year engineering student. I'm very keen to learn VHDL and FPGA synthesis. I believe choosing a final year project involving VHDL synthesis will help me a lot to learn more about it. ...

fpga vhdl xilinx

asked Nov 27 '13 at 14:42

Chanuka Perera
153

-1

votes

2answers

129 views

Confusion over clocks in FPGAs / Verilog

I just purchased an FPGA and I am learning Verilog but I have run into a few confusions, most of them regarding the clock. My first question is, how does sequential logic work? Are the assignments ...

fpga verilog clock

asked Nov 24 '13 at 2:51

Big Endian
39917

0

votes

1answer

65 views

Reading an Image file on FPGA for processing

I am trying to implement image processing on FPGA. I need to have an image for testing my module. I tested the module for single bit, by just generating a pixel value on test bench, but would want to ...

fpga

asked Nov 24 '13 at 2:36

Sherby
70912

-2

votes

2answers

85 views

Trouble with expansion connector pins in spartan 3 fpga

I know how to turn on the fpga LEDS using push buttons and switches. I'm still having trouble figuring out how can I receive a signal from the buttons to the expansion connectors. Also, how should I ...

led fpga switches xilinx spartan

asked Nov 23 '13 at 19:59

EMPV
1

1

vote

1answer

137 views

Strange noise on DDS

I have built an FPGA based DDS (fc=200MHz. out: 0-50 or 0-80 MHz) . I have a decent DAC output wave and now trying to build an appropriate filter for it ( Fig-1 ). The filter works rather fine but ...

fpga filter noise dds

asked Nov 23 '13 at 13:04

Aug
26514

0

votes

0answers

26 views

How to vary the supply voltage for XS40-005XL board?

I have a lot of XS40-005XL boards (http://www.xess.com/shop/product/xs40-005xl/). I know these boards are really old, but they are still functional. So I decided to do some experiments on them. What I ...

power-supply fpga voltage-regulator xilinx programmable-logic

asked Nov 22 '13 at 16:47

abc
183

0

votes

1answer

174 views

FPGA Board to buy? Nexys3 or Nexys4

I was considering buying a Nexys board to learn about digital electronics. The famous ones I see are the Nexys3, and Nexys4. Can someone suggest based on usage, which is better. Also, some other ...

fpga

asked Nov 21 '13 at 22:17

Sherby
70912

1

vote

1answer

60 views

why fork- join is not supported in ISE Webpack?

I am using the newest version of Xilinx ISE Webpack(v14.7). every time I try to use fork-join statement ( in Verilog ), I receive this error: ERROR:Xst:850 : Unsupported Fork Statement. Is this ...

fpga xilinx ise

asked Nov 20 '13 at 11:11

Aug
26514

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