Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.
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Bit compression in Verilog
I am trying to write a Verilog code for a multiplier based on the abacus principle. I want to compress an array of 8X15 bits to the lowest rows. For e.g. for an array of
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37 views
Verilog Iterative Circuit
I found this description in a book for a magnitude comparator, and I don't understand the explanation or why it works. I have commented everything I did understand, but that one line there just kills ...
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1answer
41 views
Understanding square braces in verilog
I don't understand what the square braces mean in the following Verilog code. Can someone please explain their purpose?
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2answers
41 views
Difference between setting up clocks on Verilog
These two statements are used quite often, to set up clocks in test benches:
initial
begin
clock = 1'b0;
forever #5 clock = ~clock;
end
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Relation between delta cycle and event scheduling in verilog simulation?
I understand that in Verilog/SystemVerilog standards there are different regions for event scheduling, thus mimicking the behavior of concurrent hardware. But how does this relate to the delta cycles ...
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81 views
What's the first step to learn Verilog coding to sort values?
I do not know how to start working on this problem. Should I first design the digital circuit of sorting? I am poor on both topic. Suppose I have four numbers R0, R1, R2, R3... What is the digital ...
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58 views
problem with CPLD and 24C16 EEPROM interface
Can any one say if it is possible to implement this code in ATMEL 24C16 EEPROM device for write the data. While I am implementing this with CPLD xc9572 I/O Pin declared as sda, scl there won't have ...
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2answers
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Please explain the following Verilog code of a D flip flop?
I am learning the Verilog language. Can someone explain the questions I ask in square brackets [] :
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35 views
Empty Netlist Vivado Design Suite
I am dealing with synthesis of verilog sources using Vivado Design Suite 2013.3 tool for the first time.
The behavior of my design is correct as verified by the pre-synthesis simulation.
My problem ...
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44 views
nonblocking statements and fork-join in verilog and/or system verilog
Can anyone please tell me the difference between non-blocking begin-end in a procedural block and fork-join. One of my friends told me that the latter in non-synthesizable and are used only in ...
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1answer
85 views
Unexpected patterns in Verilog $random
I have a Verilog test bench that monitors a 64-bit bus and should randomly schedule a flipped bit (packet corruption) to happen every 1-in-X packets. I was surprised to find it not injecting any ...
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101 views
Online FPGA/HDL synthesizer
I recall seeing a web-based HDL synthesizer a couple years ago, but I can't find it anymore. I believe it was just a frontend that ran the vendors' synthesis tools on the server.
Does this sound ...
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89 views
Connected to Multiple Drivers Problem Verilog
After I synthesize it, the error occured like this:
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what circuit the following verilog code produce
I was learning Verilog. I was posed by the following code and asked what the following code realize i.e., the circuit implemented.
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69 views
What does the following Verilog code realize
I was learning verilog hardware description language. I was confused a bit with the blocking and non-blocking statements. Can someone tell me what the following verilog codes realize and simple hints ...
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63 views
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181 views
Implementing parallel CRC in verilog
I am trying to implement a parallel CRC in Verilog but having trouble getting it to work. This is a snippet of the code that I'm having trouble with.
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1answer
60 views
High Level Language to HDL [closed]
I need to convert a simple program (C or Java) to HDL (especially Verilog). However, I have no idea about this conversion.
Another problem is that the resulting code must be gate level. Now, This ...
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1answer
52 views
Constraining the reset line
I am using Quartus II to compile my Verilog design, and I'm working to properly constrain my signals.
I know how to constrain clocks, for example:
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3answers
159 views
Setting FPGA pins as virtual
I have a Verilog module for which I want to check its timing in isolation to the rest of the system. The problem is that the FPGA has a limited number of physical pins, and my module has more inputs ...
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58 views
Difference between blocking and nonblocking assignment Verilog
I was reading this page http://www.asic-world.com/verilog/verilog_one_day3.html when I came across the following:
We normally have to reset flip-flops, thus every time the clock makes the ...
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2answers
129 views
Confusion over clocks in FPGAs / Verilog
I just purchased an FPGA and I am learning Verilog but I have run into a few confusions, most of them regarding the clock.
My first question is, how does sequential logic work? Are the assignments ...
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1answer
55 views
Verilog syntax question
Something like this:
a=b?c:d ;
would make a=c, if b=1,
else a would be made equal to d;
But what would doing the same thing on an array do?
Like this:
assign a = (|b[10:8])?8'hff : b[7:0]; // to ...
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3answers
80 views
Veriog:How to pass a register to a module?
Assume we have a module with 32 bits output like this:
module ModuleLow(foo,...);
output [31:0] foo;
Now we want to use it in another module ( a very simple ...
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3answers
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How is the assignment squence in Verilog?
I want to know if we assign something to a register ( or do anything else ) in a specific clock cycle, this assignment is performed in the current clock cycle or the next cycle? (Setting: Xilinx , ...
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78 views
How to use “Arbitrary” Vref in FPGA?
Assume we have a simple Verilog module with 1 input (in1) and one output (out). Please look at the truth table at the end of this question.
I want to send a signal with the voltage between ...
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2answers
107 views
Rounding Methods in IEEE
I am trying to learn the features of IEEE rounding from the following source On fast IEEE Rounding
Can anyone one explain the equation for round up ? What does round up with fix up mean ? And what ...
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1answer
59 views
Arithmetic shifting in verilog
I am going through the book Verilog HDL by Samir Palnitkar.
I see that there are two types of shifting, the normal and the arithmetic.
But I was not able to understand the difference between them.
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1answer
147 views
Flip flop with load/set, reset, clk, and input
I'm not looking for a hardware language description of the flip flop, but the logic gate level to implement.
In verilog, the equivalent I'm looking for is
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218 views
How to assign a pull-up/down resistor in Verilog for inputs?
As a newbie in FPGA world, I realized that it is possible to set pull-up/down resistors in Verilog but I don't know how.
I have written my code that works just fine but when I connect my XC3S400 to ...
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3answers
84 views
Using a Mux to switch between reading and driving a wire
I have been doing some googling and cannot seem to come up with an answer for this. The way I understand a mux is that it is basically a 2 way switch. I understand it is mostly used to select inputs ...
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1answer
118 views
what is BUFGP used for?
I'm trying to do some verilog code for my class and I came around BUFGP. After doing some research I only found that it is a buffer for driving clocks. Can anybody explain this to me.
For example I ...
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2answers
210 views
Why my FPGA programs does not work?
I am very new to FPGA and sorry for this elementary question. I just made a very simple XOR code like this with Webpack ISE to download to XC2S100 ( just for test!) but it does not work.
EDITION1: ...
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46 views
verilog file with own library import into cadence
I need to import a verilog net list file into cadence. I'm writing the verilog file with my own developed application. I defined several library elements inside the net list file which are not part of ...
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646 views
Control 4 digit 7-segment (2 digits number each) using Verilog
How to program using verilog, where i want to control 4 digit 7-segment display, that will show 2 digits number for first and second 7-segment display, and the others with 2 digits number too. I know ...
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2answers
136 views
pipeline and verilog
I am having a pipelined scheme and I want to have a register at the output for my result.
So, I am using this code:
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1answer
50 views
Adding Delay to Verilog Timing
I have a timing code, and on a trigger event,there is a 5 second countdown to activate a motor. Is it possible to add a delay of half a second in activating the output, or in the start of the ...
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53 views
Verilog - Iterating Over All Cases In Testbench
In coursework, we are creating multiple circuits and explicitly testing every single case in Verilog. The way that we have been writing test benches so far is the following:
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46 views
Moore Machine Statement in Verilog
I was going through a Verilog code, and came across this:
assign a= (b==c);
Can someone tell me what it does?
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2answers
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using ram verilog instantiation
I have implemented ram Verilog module. I made its instantiation and read the data from some address .After that I want to write the data to other address.
looks that I don`t need to made the ...
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Signal is missing in the sensitivity list and expression truncation
For the following module I get several warnings ,can you advice me how to solve them?
Line 22: Result of 17-bit expression is truncated to fit in 16-bit target.
Line 25: Signal missing in the ...
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Problem with warnings in Xilinx tools [closed]
I am interfacing a VGA monitor with Spartan 3e kit. I have a problem in the code and I'm getting many warnings, as shown below.
Could anyone explain the warnings?
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239 views
non-blocking assignment does not work as expected in Verilog
I have a very simple Verilog code and it does not seem to work as expected:
Here is my code:
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3answers
307 views
How can the number of clock cycles required to complete an instruction in a pipelined processor less than pipeline latency?
I am not new to computer architecture but I have only academic experience with micro-architecture implementation.
I have heard and read this many times but never really bothered to understand the ...
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1answer
110 views
Help with $readmemb
I have three variables, x,y,z which acts as an input to my SV model. Each of the input are of 16bit length binary data and I have 500 values of them. I need to supply them as input to my module at ...
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2answers
298 views
How to compare two numbers (nets, variables, constants) in Verilog
I am new to Verilog, and would like to learn how to compare two numbers. For example, let's compare a parameter or reg (say a) with the number 2 (2'b10). How this will be written in Verilog?
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1answer
50 views
Part select in verilog
I am a bit confused because of a odd situation in part select operator in verilog. I had read about part select and vector part select operators. But there is a situation where I am having ...
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32 views
IRSIM “switch level simulator examples”
I am trying to find out IRSIM , a switch level simulator, some more examples, else than those given in tutorials but i am unable to find so.As per my study, IRSIM is a switch level simulator which ...
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4answers
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Why FPGA's have latches when they are almost never used?
This question is a follow up question of the existing question: "When is using latches better than flip flops in an fpga that supports-both".
If use of latches in FPGA's is limited to rarest or rare ...
