Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.
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2answers
54 views
Understanding Combinational Feedback Loops
1) Please give me a simple example of a verilog code that results in combo feedback loop.
2) Why are these feedback loops undesired in your design? ...
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1answer
857 views
Connecting Altera de2 to a sensor via UART
Is Nios II required when implementing UART core using the SOPC? (or a default Nios is included) I tried writing my own module for the uart connection but it didn't work out. I need a method to ...
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1answer
54 views
Single Die Roll Counter Wrap Around Nested Ternary Conditional
I have to emulate a single die roll, therefore it needs to wrap back to one at 6.
`D1 and `D6 correspond to my 3-bit state ...
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1answer
34 views
Send signal from one output connected to multiple modules
Hi I am learning verilog and I am trying to find an answer if I have an output of type reg in a main module connected to the inputs of multiple modules, how in verilog would I specify which module I ...
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1answer
43 views
Verilog to spice using v2s- specificing the port order in the command v2s
I was trying to convert from verilog netlist into a spice netlist using the option v2s. Can I specify the pattern in which the ports will be arranged in my ...
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1answer
201 views
Inputs are are not able to force to DUT in Testbench
I have written tb in verilog. My testbench inputs are going at high impedance i.e. zz. My dut is not able to force stimulus.Please help me as I m not able detect the problem in my testbench.
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1answer
339 views
Verilog interfacing with C#
Right now, I am taking a course on Verilog HDL, however, our instructor gave us a machine problem wherein we are required to implement a program using verilog while having C# as our main gui. The ...
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1answer
410 views
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117 views
Input pins in top module unconnected
I have a problem connecting different modules in a top module. I want to do a very simple PWM using a counter and a comparator.
Counter:
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0answers
108 views
problem with CPLD and 24C16 EEPROM interface
Can any one say if it is possible to implement this code in ATMEL 24C16 EEPROM device for write the data. While I am implementing this with CPLD xc9572 I/O Pin declared as sda, scl there won't have ...
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0answers
931 views
How to assign a pull-up/down resistor in Verilog for inputs?
As a newbie in FPGA world, I realized that it is possible to set pull-up/down resistors in Verilog but I don't know how.
I have written my code that works just fine but when I connect my XC3S400 to ...
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0answers
107 views
verilog file with own library import into cadence
I need to import a verilog net list file into cadence. I'm writing the verilog file with my own developed application. I defined several library elements inside the net list file which are not part of ...
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0answers
36 views
How to use for loop inside a case in Verilog
Whether I can use for loop inside a case statement in Verilog?
I am writing code for 8-bit memory using Verilog in which I have to execute 3 conditions. They are:
Writing and reading data from 0th ...
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0answers
29 views
Altera Quartus II: FPGA .sof file corrupt all the time
Problem Background:
I have a synthesized design using Quartus II 14.0
Output file its in .sof format, to program an Altera Cyclone
It works correctly on my computer
I can load the file to the FPGA ...
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0answers
25 views
Verilog Concatenation Setting LED'sin casex
If I have a casex statement and I have something such as
{`idle, `left}: {next, LED} = {`state1 ,`turn1liteON };
and LED corresponds to LEDR[7:0] and ...
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0answers
67 views
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0answers
53 views
Routing errors when trying to implement PLL onto Spartan-6 FPGA board
I am attempting to synthesize and implement the reference design that is linked to in the 'Reference Design Additional Information' section of the following document.
I get the following error ...
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0answers
24 views
Synthing HDL down to waveform-testable format using Synopsys
I've worked a bit with the Quartus II toolset to create small systems that I could construct in Verilog and then test by applying a waveform. Then I could check the output against a Golden Waveform to ...
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0answers
47 views
How do I duplicate data from a text file into registers?
Let's say I have text file containing 8 bits of data on each line, up to 128 lines.
The design should be synthesizable and the text file is a placeholder for some buffer. The contents of that buffer ...
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0answers
58 views
How do I minimize the size of a 3-input parallel adder?
Currently this alu uses 24 logic elements, most likely from the adders. I'm wondering if there is any tool in Altera/Quartus I can use to minimize this? For my design, multiplier and RAM modules are ...
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0answers
74 views
nonblocking statements and fork-join in verilog and/or system verilog
Can anyone please tell me the difference between non-blocking begin-end in a procedural block and fork-join. One of my friends told me that the latter in non-synthesizable and are used only in ...
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0answers
39 views
IRSIM “switch level simulator examples”
I am trying to find out IRSIM , a switch level simulator, some more examples, else than those given in tutorials but i am unable to find so.As per my study, IRSIM is a switch level simulator which ...
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0answers
77 views
Verilog generation for DDG
I should generate the verilog code for high level problem specification,provided as
DDG (data dependency graph).The nodes of the graph represent inputs or output interfaces or operations ...
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0answers
139 views
Error generating simulation file: ldbanno: design file _map.ncd not found
This is what I am trying to simulate using Active HDL in Lattice Diamond
module andd(a,b,c);
input a,b;
output c;
assign c=a&b;
endmodule
When I am ...
