About tools to simulate circuits. Specify the tool used.
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26 views
Circuit simulation problem dealing with transistor operation
Simulating the circuit below (PMOS charge pump; doubles the input supply), all the transistors are operating in cutoff region when I extracted the .dp0 file. What might this means? I'm using SYNOPSYS ...
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1answer
47 views
Simulating a circuit consisting of MOSFETs
When simulating a circuit consisting of mosfets, when can you say that the MOS should be in cut-off, saturation. or linear (triode) region?
Specifically a charge pump circuit utilizing PMOS.(refer to ...
1
vote
2answers
80 views
Op-amp differentiator and integrator circuit: resistor and capacitor values
I don't understand how to determine value of resistors and capacitor in differentiator and integrator circuit of Op-Amp.
I tried to align the amplitudes of these sine waves. I keep changing their ...
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votes
1answer
36 views
PSpice Op-Amp sawtooh wave
I've got this homework about PSPice and op-amp.
I need to make this triangular waveform and sawtooth(?) waveform of non-inverting op-amp circuit.
I know the triangle one is 500us like the picture. ...
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1answer
54 views
D flip flop simulation: which simulation output is right?
I have always wondered, what is the right solution to the D flip flop when the input changes right at the rising edge of the clock? I have found two solutions of these online but have no clue which is ...
0
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1answer
49 views
Trying to understand what is needed for simple circuit simulation [closed]
I'm working on my Capstone project and a major component of it involves designing a circuit that works with the IOIO-OTG, some motors and a battery. I'm trying to find a free circuit software that ...
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0answers
17 views
Disable display in Synopsys VCS
I am currently simulating this large piece of verilog that is full of $display commands for debugging.
I believe this is making simulation slower so I want to get rid of most of those.
Is there a way ...
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0answers
27 views
How to create JK flip flop in proteus 8
I want to create a JK flip flop in Proteus 8.0 ISIS simulation tool.
This is what I tried, but the problem with this is that the outputs Q and Q' are always zero regardless of what I set J or K.
...
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1answer
62 views
What is wrong with this PSpice simulation?
I am trying to simulate this circuit on PSpice as my first PSpice homework, I'm required to learn to simulate circuits on this software.
From calculations, we know that:
Ix = 16 A.
Current ...
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0answers
23 views
How to get OpenCL kernel simulation performance by Altera OpenCL SDK or Quartus II?
I am using OpenCL to program FPGA by Altera OpenCL SDK. However, I don't have an Altera FPGA board now. Thus currently I just want to do emulation or simulation to get performance like number of ...
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0answers
19 views
Is it possible to create a custom animated component on Proteus ISIS?
I'm using a subcircuit block, where the inside circuit is like this:
When i simulate the circuit in the main sheet, i have to use the "go to child sheet" command to see if the LED D5 is illuminated ...
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0answers
38 views
Find IC's Model file (*.MDF) for Proteus
I have a circuit design and I want to simulate and test it on Proteus before implementing it.
But some of ICs which I've used give me errors when start simulation.
The error was ...
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0answers
38 views
Real world efficiency of a LM3150 Webench DC power supply design?
When designing a DC/DC step down converter with TI Webench with these parameters:
Vin min: 11.4 V
Vin max: 12.6 V
Output : 5.0 V
Iout : 8.0 A
Ambient temp: 30 ºC
Then turn the efficiency knob ...
2
votes
1answer
40 views
LTSpice Level 2 Simulation CMOS follower
I'm trying to make a level 2 simulation of a voltage buffer made by a CMOS circuit:
For this, I have been told to use level 2 CNM25 technology Spice models for the transistors, and I have been ...
1
vote
1answer
89 views
8 Transistor Full Adder
I am working on 8 Transistor full adder which is based on 3 Transistor XOR cell.
I have studied many IEEE Papers for 8 Transistor Full adder. All have same ckt as above.But the full adder is not ...
0
votes
1answer
44 views
Problems with OpAmp based amplifier simulation
I'm trying to simulate a simple amplifier for an electret microphone, but having problems regarding the output level and virtual ground.
The circuit in Multisim is as follows:
What I'm having ...
1
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0answers
37 views
Snubberless TRIAC not turning on in negative cycle
I have a simple circuit with a MOC and Snubberless TRIAC.
I am using the ST Snubberless Library for my simulation.
I cannot understand why the TRIAC does not turn on in the negative half cycle, even ...
1
vote
1answer
71 views
How to design a SPICE model from data sheet?
I am new to SPICE simulation and I am looking for spice model file of LTC 1065 data sheet can be found here here.
I searched a lot on Google but I could not find ...
8
votes
1answer
411 views
Why doesn't my opamp relaxation oscillator oscillate?
I have designed a relaxation oscillator with an opamp. It is supposed to oscillated at 50Hz, but it doesn't. I haven't built a physical circuit, I'm trying to simulate it in CircuitLab.
I calculated ...
0
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0answers
19 views
How do I specify a parameter for a specific component in LTSpice?
I have a schematic which uses two center-tapped transformers. I found that I can specify the ratio between the two sides of the transformer by adding the directive ".param ratioT=0.3".
Now that I ...
1
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0answers
67 views
Piezo & RFC Modeling! [closed]
I want to model the circuit in the picture below. It is an ultrasonic humidifier.
But I can't model it for two reasons:
The inductor on emitter is a RFC (radio frequency choke).
There's a crystal ...
0
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1answer
39 views
Problem simulating FSM in Quartus II Simulator
I am trying to simulate a FSM using vector simulator...
the state machine variable is called "Tstep_Q", I added it to waveform editor... however, when I start the functional simulation
all signals are ...
2
votes
4answers
207 views
Simulating Smoothing Caps in TINA
I'm trying to simulate the workings of smoothing capacitors in TINA-TI. I have a varying voltage source (sine wave varying from 4.5-5.5V) and 2 capacitors (1uF and 100uF) connected. The load is a 1000 ...
1
vote
1answer
102 views
How to simulate PCIe to debug my FPGA endpoint
I'm working on an FPGA controller connected through PCIe. The only way I can debug the hardware is using chipscope. So I execute commands through my driver and check out the signals from the FPGA.
...
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3answers
86 views
Alien circuit component
I am modeling chip MC14538 in PSPICE by building its internal circuit from the datasheet. I, however, can't figure out what ...
0
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1answer
74 views
Help understanding the behavior of an RLC circuit
I am trying to generate a transient pulse (time to peak T1 = 6us; time to fall to 50% of peak T2 = 70us) with an RLC circuit. The cap is first charged and then discharged through an LR circuit. I ...
3
votes
2answers
215 views
How can I simulate a bridged output of a speaker at 8 ohms?
Following on from my previous post on a single 5V rail amplifier, I'm trying to simulate a bridged output op amp set up to drive an 8 0hm load.
One of the solutions was:
Use a bridge output. This ...
0
votes
2answers
75 views
Why am I not able to simulate a circuit as it is given in a problem?
I'm currently in the process of working through some circuit analysis books on my own. Though it's easy enough to compare my answers to those given in the appendices, I figured that it would be ...
0
votes
1answer
34 views
Changing the duration of a pulse in PSPICE
I am trying to simulate lightning in PSpice using an exponential voltage source (VEXP). The duration of the lightning pulse is required to be in the 110-120 microseconds range with peak voltage = ...
0
votes
1answer
43 views
What does “no design unit detected in this file” mean?
I got this error then I tried to add a source file.
Can anyone tell me what this means? What should I do to correct it?
0
votes
2answers
43 views
Debugging simulation error in Xlinx for VHDL
I used Xilinx to simulated Logic And Gate, and it worked fine. I followed same procedure to simulate Half-Subtractor, but got stuck in between.
When I checked Xilinx window for two codes I found ...
0
votes
1answer
147 views
How to make a simulation for wireless power transfer circuit in HFSS (High Frequency Structural Simulator) software?
I want to simulate a circuit of wireless power transfer consisting of two resonating coils along with a loop with each coil. I am stuck with introducing a coil in HFSS.
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2answers
45 views
Is there any simulation software that can be used for simulation circuits of wireless power transfer?
I am searching for a simulation software that also shows the interaction between electromagnetic waves in a wireless power transfer setup.
0
votes
1answer
66 views
Current sink - work in simulator, doesn't work in real
I've built current sink to drive wheatstone bridge. I've counted that I must reach current ~0.2mA to properly working whole measure system. Picture below present my current sink (I use MCP6001 op ...
2
votes
2answers
88 views
ngspice, malloc: internal error can't allocate -8 bytes
I am new to ngspice and trying to simulate my first circuit. I have posted my spice.net and my simulation.cmd below with a picture of my schematic. When I run the simulation I get the error message:
...
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0answers
28 views
what is the difference between continous phase FSK and discontinous phase FSK? How do their outputs look?
I simulated the output of both the cases in simulink but not able to differentiate.
The above shows the output for the continuous fsk, please see the figure for values of mask parameters.
The above ...
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0answers
27 views
simulate QPSK using simulink
I have tring to simulate QPSK system using simulink , so i choose from workspace block , to enter the data into the system , but when i have simulate it , an error ...
0
votes
1answer
83 views
How to correctly edit a system to increase per-unit voltage of a bus [PowerWorld Simulator]
I have created and simulated the following energy system using PowerWorld Simulator 17 (please download the picture if it's not clear).
Now, I was given the requirement that every bus should have ...
0
votes
1answer
40 views
Inverter not showing the right output in HSPICE
This is the code snippet apart from the usual headers in the rest of the file:
...
0
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0answers
50 views
How to connect a simpowersystems components with simelectronics?
I am doing a project in synchronous generator and I am using comparator from the simelelectronics and using simpowersystem components to connect each other. There is a problem in connecting the ...
0
votes
2answers
85 views
Quartus Gives Undefined Signal For the State of a Finite State Machine. Supposed to Be Showing Enum of the State_type
Before beginning a larger project in Quartus II I'm trying to do the section 8.8 "FSM as an Arbiture Circuit" example from the book "Fundamentals of Digital Logic with VHDL Design 3rd ed" and I can't ...
0
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0answers
99 views
Project to Print School ID on a 7 Segment Display - All Segment Outputs are High When Simulated
I am working on a project that uses a BCD up-counter block, a BCD to school ID block, and a BCD to 7-segment display, in order to print out my school ID on the 7-segment display of an FPGA.
Here is ...
0
votes
2answers
105 views
BCD Up-Counter Schematic Error
When I try to simulate my schematic for my up counter, i get the error
Net "Net-name" cannot be connected both to an input port and an instance output pin.
Here is my schematic
I am pretty sure ...
0
votes
1answer
51 views
Cadence SoC encounter
I am trying to create the layout of my design for an 8 bit multiplier accumulator in SoC Cadence encounter tool. After routing the design using wroute command, the ...
1
vote
0answers
81 views
How to create Spice / LTSpice repeatable damped sinusoid
Is there a more elegant and/or simpler method to model a repeating, damped sinusoid from SPICE or LTSpice rather than chaining the damped SINE sources in series? Below is a schematic and the ...
1
vote
2answers
384 views
Can you interface a Modelsim testbench with an external stimuli
I am working on a team that is doing both driver software and FPGA development. The FPGA simulation is being done in Modelsim and driver software is written in C. To minimize integration risk, I ...
0
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2answers
190 views
How to simulate Wi-fi signal strength indoor environment?
I want to simulate Wi-fi signal strengths received by a mobile moving around in X m3 that contains N access points. I must take into account the effect of walls and if possible the effect of moving ...
1
vote
1answer
69 views
Does NI Multisim simulates op-amp input and output noise?
I just created a circuit with AD620 in-amp and I'm worried that there is not enough noise.
I wonder if Multisim simulates advanced op-amp/in-amp properties, like input noise and such?
I mean, if I ...
1
vote
0answers
267 views
Wien bridge oscillator LTSPICE
im looking for a good oscillator to implement in a circuit and I was trying to simulate a Wien Bridge oscillator in LTSPICE but I have no success as my output is always 0 V. Is there a special ...
-1
votes
1answer
84 views
Is there any online or free to download (for Windows 7) AVR simulators? [closed]
I'm currently using CodeVision AVR to write a code. Let's say I have a compiled HEX file and I'd like to try it running on a virtual processor (ATtiny861A).
Google gives me some results but I'd ...
