A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".
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17 views
VHDL USB UART Problem
I've just described an UART transmitter and receiver in VHDL. In simulation everything seems to be fine. In FPGA, the loopback interface works well: I push a button, the transmitter sends data, the ...
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20 views
Using nRF8001 as a master with an FPGA
I would like to use Nordic's nRF8001 modules in Master and Slave modes and also would like to connect it with Spartan-3E FPGAs using SPI. I am considering buying the nRF8001 DevKit.
I believe it is ...
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0answers
55 views
FPGA board with multipe FPGAs [on hold]
I am very interested in Numerical computations using FPGAs. Are there any boards that have multiple FPGAs? I don't need any GPIO's or other type of inputs. All I am looking for is to program the chips ...
5
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1answer
342 views
Transceivers in the field of FPGAs: When and why will we use them?
I am recently getting myself into the field of FPGA design and development, and lately I've found myself hearing a lot about transceivers. I tried searching the net for some answers about these ...
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2answers
745 views
How can a microcontroller be more efficient than an FPGA?
If we don't count the cost of both (MCU, FPGA) are there any applications where a microcontroller can be more efficient than an FPGA? It is easier to program a microcontroller than an FPGA (embedded C ...
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34 views
Digital Buck Control
I wish to emulate a voltage mode buck control using FPGA.
My idea was to obtain a discrete state space equation that can be implemented digitally.
At first I calculated to the buck small signal open ...
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1answer
57 views
OLA adder and signed digit vhdl design problem
I have implemented the following online adder for signed digit using vhdl code
and I have simulated my design according to the example table shown in the figure attached
the problem is I am not ...
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1answer
44 views
External MMU for cortex-M
The Cortex-M processors are getting faster and more powerful. The Cortex-M7 has just been announced. Yet these cannot run Linux (other than uCLinux) because the chips lack an MMU - Memory Management ...
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24 views
Integration of Pulse Generator Module with FPGA
How can I get the number of pulses from a variable frequency pulse generator module through FPGA or how to integrate a pulse generator with FPGA in order to get the number of pulses?
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2answers
72 views
Uploading C program to the ARM core for execution through ethernet!
I want to write a c code on my local PC and upload it to ARM core on Zed-board for execution. I know we can do it using JTAG, but for obvious reason I want to use Ethernet interface.
I will be glad ...
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2answers
60 views
How can an input signal to an FPGA be determined as the clock signal?
How can I determine a seemingly arbitrary signal applied to an FPGA to be the clock signal? Conditions: 1. There is no other clock signal available (as an input to the FPGA) for sampling this input.2. ...
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2answers
52 views
Transmitting HDMI/DVI over an FPGA with no support for TMDS
I'm hoping to be able to output HDMI/DVI-D for my next FGPA project but my FPGA doesn't have native support for TMDS outputs. The FPGA is a Spartan 3E and I believe it only has support for LVDS ...
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2answers
88 views
Selecting an external crystal for FPGA
Assuming that the FPGA has a clock multiplier to get much faster frequencies internally, what is good choice for an external crystal? Let's say I've got a Virtex 7 class FPGA, and I plan to run ...
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2answers
91 views
Online arithmetic with radix 2 addition
I am having trouble working with OLA(online arithmetic addition) radix 2 SD(signed digit) addition MSDF(most significant digit first).
If I have an 8 bits range unsigned number and a redundant and ...
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2answers
136 views
Interfacing FPGA and a storage device
I'm doing this project called "High data rate logger".
The requirements for this project is to sample the 2 analog signals simultaneously.
2x channel 14-bit ADC
Store 60 MSps (mega samples per ...
4
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3answers
77 views
VHDL: Using '*' operator when implementing multipliers in design
Present day FPGAs have built in DSP blocks, the latest FPGAs even have built in IEEE-754 compliant floating point units.
It is possible to create DSP entity/module using a GUI after selecting the ...
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1answer
101 views
50 MHz FPGA (Cyclone IV @ DE0-Nano) and 60 MHz input from FT2232H
I want to read data from FT2232H used in an FT245 style synchronous FIFO mode (http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf p.27) with DE0-Nano FPGA board:
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2answers
110 views
Homebrew Computers - TTL/FPA computer that can run a POSIX OS? [closed]
The internet is filled with inspiring examples of homebrew computers, including ones made from relays and TTL gates.
In the first year of Make Magazine - they describe a person who builds a simple ...
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1answer
26 views
Report entire failing path in Quartus
I am trying to optimize a design that does not meet the constrains.
I know that you can use Timequest Timing Analyzer -> Report Top Failing Paths to report the paths that have negative slack but it ...
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0answers
41 views
2 Transistor 2:1 MUX with negative waveform
My PTL(Pass transistor logic) 2:1 mux show -ve waveform at at some inputs combination ckt and waveform show below:
simulations perform at 180nm tech, 250mhz,1.8v power supply. How to cope this ...
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1answer
69 views
How to protect FPGA from relays?
I'm preparing for a project that will interface an FPGA with many 3v relays on its gpio. Additionally, some of the relays will be powered with the same power supply that the FPGA uses. The FPGA will ...
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67 views
How does the read & write FIFO of the Xilinx work?
I'm having a problem understanding the mechanisms of the read FIFO and write FIFO of Xilinx IP core generator (in the Xilinx platform studio software). I don't understand how the read FIFO sends data ...
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2answers
134 views
How many IP can I fit into an FPGA?
How can I calculate if a certain IP will fit into a certain FPGA?
If the unit of measurement of an FPGA size is the LUT, I need that FPGA lut >= core lut
For example, can I put a S1 core (37k look up ...
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60 views
Vivado optimizing away my pins
I'm fighting Vivado over what seems like a fairly stupid issue to me. I wrote some Verilog code in ISE (and simulated it). I generated a bitstream in ISE and downloaded it onto the board via impact, ...
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94 views
Understanding timing constraints
I don't want an introductory text on timing constraints, nor an application note, an user manual, a webinar. I read them all, already, many times. The concept behind timing constraints is very easy. ...
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3answers
190 views
custom FPGA PCB Design tips
I am planning to design a custom FPGA PCB. the PCB will contain sensors. I need to read the output of the sensors and process them in the processor. I have completed many projects using FPGA's, but ...
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1answer
129 views
counter that MSB toggles every 2 seconds [duplicate]
I want a counter that the Most significant bit toggles every 2 seconds, and gets values 0 and 1.So for example it will have 0 for 2 seconds and after 1 for another 2 seconds etc..
I need it like that ...
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0answers
96 views
Explanation of performance graph of FPGA design
After implementing a mathematical function on a FPGA chip. The following graph shows for ~40 inputs the time response, i.e. how long it took to get the output calculated. This data is part of the ...
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2answers
39 views
Altera III Cyclone FPGA input synchronization problem
I have a problem with the asynchronous input signal synchronization. I am trying to make the IIC_Slave based on Cyclone III FPGA Starter Kit.
I saw 3 cases:
1) If I not use synchronization ...
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0answers
143 views
Bidirectional FPGA implementations (parallel ADC)
New FPGA convert here. I am trying to interface with a parallel ADC as part of a data acquisition project. The pins on the ADC are used for both input and output (not simultaneously). Therefore, I ...
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1answer
57 views
Xilinx Video Timing Controller freezes processor
I'm trying to acquire video from an image sensor using a ZedBoard with Vivado 2014.2 and I used an existing (working) video passthrough project of mine and simply added in a debayer (color filter ...
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1answer
89 views
2 Transistor XOR Cell Floating Output Problem
I designed the following 2T XOR cell for my full adder purpose:
Theoretically it gives correct output for all input combinations. But on Tanner Eda using 180nm technology 5V supply, it gives logic ...
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2answers
80 views
Strange I2C signals emitted from FPGA
I have a ZedBoard FPGA device and I'm trying to implement an I2C interface to communicate with a camera module. I'm using Vivado 2014.2 and I have added an AXI IIC block to my design with the SCL ...
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1answer
86 views
FPGA outputs are always high with basic and/or program
So I am just getting started developing with an Altera Cyclone II EP265 mini board, and I am having some trouble getting a program that outputs the "and" and "or" of three inputs working.
The full ...
4
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1answer
84 views
Configuring a 7-Series GTXE2 transceiver for Serial-ATA (Gen1/2/3)
Hello this will be an experts questions :) You should be familiar with the following topics
Xilinx Multi-Gigabit-Transceivers (MGTs), especially the 7-Series GTX/GTH transceivers (GTXE2_CHANNEL)
...
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2answers
103 views
FPGA RAM / SRAM in VHDL
Today I ran out of gates on my Xylinx Spartan 3 (Basys2 by Digilent) FPGA.
This was not a surprise to me as I had implemented an 8 bit x 2048 array for use as an FIFO buffer.
Code: ...
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2answers
117 views
FPGA Systems with good Linux support
I am working on a project using a Xylinx FPGA, board produced by Digilent. More precisely, it is the BASYS2. I have been programming the FPGA using Windows 7 as I was unable to install the support ...
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2answers
104 views
Synchronizing input and output
How do I synchronize this system? The data valid at the input indicates when the data is valid at the input. Similarly the data out valid indicates when the output data is valid. Both ...
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2answers
103 views
How do you set the time resolution in Synplify?
I am generating a 1khz pulse from a 32MHz clock, naturally via a counter. Not a difficult task, so you can imagine my surprise when the result runs at 992Hz...
Simulating the behavioural model of ...
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4answers
76 views
Outputting a clock signal from an FPGA
Referring to question here: Click here, I'd like to use the 16 channel LED driver to run my 7-segment displays. I'm using a Spartan 6 LX9 FPGA to implement a 16-bit microprocessor that will take care ...
4
votes
3answers
112 views
Can a barrel shifter be done combinatorially?
I was told that 66b/64b encoding in 10Gb Ethernet (10GBASE-R) requires a one-cycle barrel stage, which adds a necessary one cycle to the theoretical terminal latency.
The Wikipedia page on barrel ...
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0answers
52 views
Altera Quartus II: FPGA .sof file corrupt all the time
Problem Background:
I have a synthesized design using Quartus II 14.0
Output file its in .sof format, to program an Altera Cyclone
It works correctly on my computer
I can load the file to the FPGA ...
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1answer
82 views
VHDL 'buffer' vs. 'out'
I was wondering about the 'buffer' i/o option for entities in the VHDL language. I have found that my code is much cleaner if I use the 'buffer' option instead of 'out' in any circumstance where I ...
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1answer
39 views
Configuration an FPGA on installation
I am working on a project using a Virtex-5 FPGA. The small projects that I've worked on with FPGAs has only required me to program the FPGAs on development boards using JTAG or loading the bit file ...
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0answers
30 views
Installation of IceCube2 on Linux
I am trying to install the Lattice IceCube2 software on my linux box (i am using Fedora 20 64bit) but i only get the message that the binary installer cannot be executed.
Does anyone know how to ...
3
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1answer
87 views
Clock domain crossing timing constraints for Altera
I have a slight problem with my clock domain crossing timing constraints.
I have two clock groups
set_clock_groups -asynchronous -group {clk_A} -group {clk_B}
...
2
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1answer
95 views
How do I reset an FPGA development board to its factory settings?
I have programmed an Altera board in configuration mode so that it runs my program when booted up. Now I want to revert it back to factory configuration. How do I do that?
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1answer
81 views
UM232H-B Breakout Module as a parallel port
I want to build something like UM232H-B Breakout Module. This configuration uses an FT232H, to convert usb to serial/parallel. I don't know whether it works with FPGA parallel port programming cable ...
2
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0answers
101 views
What is bit-true implementation
What is bit-true implementation (with an example if possible)?
I was reading a paper and it was stated "a bit-true implementation of the algorithm on a FPGA was performed." So what exactly is ...
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2answers
323 views
Reading the program off a FPGA
Suppose I have some sensitive proprietary software (VHDL/Verilog) on an FPGA connected to my server so I can control it by SSH. Now suppose an attacker compromises my server and can communicate with ...
