In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.
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806 views
What is the difference between testing and verification?
Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction.
To ...
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3answers
630 views
Why delays cannot be synthesized in Verilog?
I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code.
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5
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2answers
118 views
Difference between >> and >>> in verilog?
What is the difference between >> and >>> in verilog/system verilog? I know that ...
4
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2answers
145 views
How to efficiently implement a single output pulse from a long input on Altera?
I have a fast clock and a switch called 'ready'. When the switch is flipped (ready goes HIGH), I would like the output pcEn to produce a pulse that lasts only for one clock cycle. pcEn will only ...
4
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1answer
279 views
How do I make use of multipliers to generate a simple adder?
I'm trying to synthesize an Altera circuit using as few logic elements as possible. Also, embedded multipliers do not count against logic elements, so I should be using them. So far the circuit looks ...
4
votes
2answers
106 views
Secure signals on boot time to prevent unwanted operations
How can I be sure that at boot time my module won't get random values to it's control signals and write to an address* before I reset the module?
*(or anything that shouldn't be done before reset)
...
3
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1answer
588 views
Systemverilog to Verilog translation
I have a code block (multiple files) in Systemverilog. I am using the Xilinx tool flow that does not understand SystemVerilog (an old part). Is there a tool (or a rule book) I can use to convert the ...
3
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1answer
119 views
System Verilog seq.ended or seq.triggered
Some verification tools support the following System Verilog code:
wire s = seq.ended;
Where seq is an SVA sequence. Other tools do not support this code. Is ...
2
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2answers
152 views
Generate flip-flops using only combinational logic
Just for fun, I wanted to design and simulate D-type flip-flops using only combinational logic in Verilog (or SystemVerilog). I am using using Verilator for the simulation.
My initial attempt, which ...
2
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1answer
77 views
Functional and Timing accuracy of an RTL Model
I am sometimes really confused by the abusive use of jargon in EDA/VLSI design articles and books. With no precise definitions, its upto the reader to make interpretation which is very ambiguous and ...
2
votes
2answers
132 views
Efficient use of space in FPGA
Background and clarifications:
I've never developed/written a single piece of hardware before, but I'm currently using Verilog to develop a huge project for a FPGA as my final graduation project.
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2
votes
2answers
253 views
Continuous assignment during SystemVerilog simulation
I am providing input to an SPI interface. The input signal is a concatenation of several different signals. What I would like to do in simulation is have continuous concatenation of the different ...
2
votes
2answers
70 views
Modelling current to remain in particular range for fixed simulation time
I am a novice in SystemVerilog. I wish to know how to model a 8-bit signal X to attain four levels for certain ranges of time. For example,let the legal values of X be from 40 to 80(40 < X < 80)
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2
votes
1answer
127 views
Random number generation
I have written this code in system verilog to generate fifty 12-bit random numbers and write them to a file.
How can I generate the random numbers in octal instead of decimal?
Also, how can I make ...
2
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1answer
67 views
Difference between HVL and HDL
Hardware description language describes our circuit but what does Hardware Verification Language do? How does it verify the design?
2
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1answer
283 views
How to reference subsets of logic[31:0] in SystemVerilog?
(I have two questions for you at the end.)
I'm using SystemVerilog to do various exercises (for personal edification) in Digital Design and Computer Architecture's chapter 7. I'm using Altera's ...
2
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1answer
93 views
Is SystemVerilog string manipulation synthesisable?
I learnt that SystemVerilog provides a string datatype, which allows for many string operations, such as comparison, concatenation, length, etc.
Are those string operations synthesisable?
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vote
2answers
42 views
What do the terms code coverage and functional coverage refer to when it comes to digital design verification
It seems that verifying a design is a more complex task than the actual design itself and takes a lot longer to carry out. We may even need to create testbench to very the original testbench that ...
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1answer
93 views
Instantiating Parameterized Modules in SystemVerilog
In SystemVerilog I would love to instantiate modules like
...
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1answer
203 views
Correctly printing from SystemVerilog DPI
I have some verilog VPI code that I'm porting to use SystemVerilog DPI, to be run in Modelsim and Verilator.
In VPI, I use vpi_printf() for debugging and status information. This doesn't work when ...
1
vote
2answers
1k views
Parameterized net width in Verilog
Is something like this possible ?
parameter width;
wire[width-1] a_net = (width)'b0;
I basically need a variable to control the width of the right hand side. I ...
1
vote
1answer
460 views
How to design a two-stage synchronizer with a clock divider in Verilog?
I have a very fast clock called CLOCK_50 which I would like to slow down through the use of a clock divider. The output is ...
1
vote
1answer
196 views
How exactly does SystemC/SystemVerilog make the verification flow less laborious task
Now days SystemC or SystemVerilog are used for verification of complex designs, especially for things like SoC designs that are really complex. I do know that these languages bring in the OOP design ...
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1answer
2k views
Instantiating multidimensional array in system verilog
I want to create an array in systemverilog which has n entries of m bits.
logic [n-1:0] arr [m-1:0]; (a)
Is this the right way to do it? What if I change the ...
0
votes
3answers
89 views
using C libraries inside verilog
I'm implementing a radio in Verilog. the time taken for bit reversal while computing the FFT is more. it is almost equal to a symbol time (OFDM system). Can I use a FFT library in C, which can be ...
0
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1answer
317 views
What is wrong with following Verilog code where I am trying to pass a one-dimensional array?
What is wrong with following Verilog code where I am trying to pass a one-dimensional array?
...
0
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1answer
66 views
Is it fine to have different number of input/output port in module and module instant in verilog?
For example if i am going to model T flip flop using D flip flop. I am not writing the whole code of T flip flop as here it is not related to my query.
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0
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1answer
81 views
Inheritance of properties
Is it possible to inherit some properties from the scope that we invoke a function? A code snippet might help more to explain:
...
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1answer
470 views
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2answers
110 views
System verilog on Quartus synthesis issue
module blockingbad(input logic clk,a,b,c,output logic y);
logic x;
always_ff @(posedge clk) begin
y=x|c;
x=a&b;
end
endmodule
For ...
0
votes
1answer
199 views
Help with $readmemb
I have three variables, x,y,z which acts as an input to my SV model. Each of the input are of 16bit length binary data and I have 500 values of them. I need to supply them as input to my module at ...
0
votes
1answer
26 views
System Verilog Adapter Interface
I am using Xilinx's PCIe Core, which in its latest version duplicates the AXI valid signal 22 times.
This means writing something like {22{1'b1}} every time I try ...
0
votes
1answer
31 views
Why the port type of this module default to 'var'?
In "IEEE Std 1800-2012 SystemVerilog", p. 668, I find this:
module mh11(output integer x); // output var integer x
I wonder why it is default to 'var' but not ...
0
votes
1answer
130 views
Spawning threads in SystemVerilog with input variables
I run onto a rather confusing situation where I was writing a code for a UVM monitor. This module performs these operations in order:
Listen to channel (virtual interface) until intercepting one or ...
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1answer
42 views
How should this code look like in verilog?
I am designing an ALU to add at state 000, I have to assign control signals for a mux, carry in, and operands so that it works. so, i wrote an if statement in the controller module, and the TA told me ...
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1answer
68 views
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2answers
121 views
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1answer
89 views
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1answer
161 views
Working of Prefix Adder
I am trying to understand the working of Brent Kung adder, but I have not been able to.
All that I see in tutorials is just the figure above for carry generation. Can anybody explain it to me with ...
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1answer
1k views
Connected to Multiple Drivers Problem Verilog
After I synthesize it, the error occured like this:
...
0
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1answer
22 views
Non overlapped implication(|=>) used in system verilog assertion
I know that if I use
s1 |=> s2
the consequent sequence expression s2 will be evaluated on the next clock tick. However, if there is no clock(combinational ...
0
votes
1answer
102 views
Creating SystemVerilog module using for loop and separate custom module
I am trying to create an n-bit barrel shifter using the diagram in the answer to this question: http://stackoverflow.com/questions/26551049/vhdl-n-bit-barrel-shifter
I've read that if the variable in ...
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0answers
19 views
Difference between >> and >>> [duplicate]
What's the difference between >> and >>> in Verilog/SystemVerilog?
I know that ...
0
votes
0answers
51 views
Verilog Concatenation Setting LED'sin casex
If I have a casex statement and I have something such as
{`idle, `left}: {next, LED} = {`state1 ,`turn1liteON };
and LED corresponds to LEDR[7:0] and ...
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0answers
84 views
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0answers
66 views
How do I duplicate data from a text file into registers?
Let's say I have text file containing 8 bits of data on each line, up to 128 lines.
The design should be synthesizable and the text file is a placeholder for some buffer. The contents of that buffer ...
0
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0answers
70 views
How do I minimize the size of a 3-input parallel adder?
Currently this alu uses 24 logic elements, most likely from the adders. I'm wondering if there is any tool in Altera/Quartus I can use to minimize this? For my design, multiplier and RAM modules are ...
0
votes
1answer
70 views
Single Die Roll Counter Wrap Around Nested Ternary Conditional
I have to emulate a single die roll, therefore it needs to wrap back to one at 6.
`D1 and `D6 correspond to my 3-bit state ...
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votes
1answer
40 views
Running UVM example on MODELSIM - ALTERA 10.1d
I want to compile and simulate this simple UVM example using Modelsim-Altera 10.1d tool.
...
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2answers
333 views
Understanding Combinational Feedback Loops
1) Please give me a simple example of a verilog code that results in combo feedback loop.
2) Why are these feedback loops undesired in your design? ...
