A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".
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22 views
2
votes
1answer
36 views
Xilinx ISE warns that a signal is trimmed since it has a constant value of 0, but the signal is used within my code
I have created the following VHDL module, which is used as an up/down counter.
...
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1answer
50 views
video wall FPGA [on hold]
I am new to FPGA systems but I want to use this platform to design a video wall (2x2) based on HDMI or VGA standard. I know it is harder than it may sound but I am in it for long haul.
To start in ...
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votes
1answer
47 views
Clock port and any other port of a register should not be driven by the same signal source
I get this Warning from Altera Design Assistant for the below:
Clock port and any other port of a register should not be driven by the
same signal source
Critical Warning (308012): Node
...
-4
votes
1answer
33 views
pixel clock generation for xga 65MHZ [on hold]
Good morning,
I am designing a xga timing generator in verilog but my problem is i am not sure how to create a pixel clock using 65 MHZ for xga specification.
Does anyone have any idea?. Thank you ...
0
votes
1answer
40 views
Altera Quartus Design Assistant Critical Warnings
I get a number of Critical Warnings with respect to lpm_ff and
lpm_counter:
Below are few:
Rule A102: Register output should not drive its own control signal
directly or through combinational ...
0
votes
0answers
41 views
Using 4-Channel ADC With FPGA
I am using an ADC084S101 4 Channel 8-bit A/D Converter to sample 4 different analog voltages. The ADC is being driven by a Nexys3 FPGA. I am having issues getting the ADC to cycle through all four ...
0
votes
1answer
79 views
IC to patch pins arbitrarily?
Is there an IC that will support patching pins together arbitrarily for AC or DC signals going in both directions across any patched pair of pins?
I'm pretty sure it could be done with an FPGA though ...
2
votes
0answers
31 views
How to specify a minimum clock to output time in output timing constrain?
In a design, an external clock pin triggers a flip-flop, where the output goes to an external data pin.
Using Xilinx ISE, how can I specify a timing constrain, so the output should be held for some ...
-2
votes
0answers
18 views
Design 2x1 multiplexer using VHDL [duplicate]
I need to design frequency for a 2x1 multiplexer using HDL for my project. The description is:
If select = 0, output = input 1 (10kHz)
If select = 1, output = input 2 (100kHz)
The problem is, I ...
0
votes
0answers
23 views
Lattice fusemap error
So today at work I got a Lattice Platform Manager development board (LPTM10-12107-3FTG208CES and I started working on a program to test it. I created the JEDEC file, opened the programmer, connected ...
1
vote
2answers
68 views
can't solve latches
I would like to ask if someone could help me with some latches in my desing. I am working with an aes encrypt core taken from opencores and I have described in vhdl the surrounding system to ...
4
votes
2answers
81 views
Dual port RAM on Altera and Xilinx FPGA
I have always managed to synthesis a 256 x 32 bits dual-port RAM (not true dual port RAM) in Xilinx ISE with just 1 x 18K BRAM.
The example code from here was used:
...
1
vote
1answer
64 views
FPGA Frequency Divider
I need to design frequency divider from 50MHz to 200Hz using FPGA. I'm using Xilinx and the language that I used is VHDL language. I got stuck because I can't get the output. So, anyone can help me? ...
3
votes
0answers
32 views
Help with multiple receiver channels and single storage architecture
I want to build a datalogger that has multiple receiver channels that run on serial communication protocol RS232 and then collect the information from the channels in a single storage that would be ...
0
votes
1answer
46 views
Could an FPGA be connected via DMI to a processor, if so how would this be done? [closed]
Can an FPGA be connected to a processor via Direct Media Interface (DMI), without a dedicated Platform Controller Hub (PCH)? The FPGA would serve as the south bridge/ PCH. Along the lines of ...
0
votes
0answers
25 views
Failure: (vsim-3808) Incompatible modes for port
I am attempting use modelsim to simulate a peak detector and am having trouble with the simulation of the handshaking protocol between two modules: dataGen and dataConsume.
I am certain that the code ...
0
votes
1answer
34 views
Generating Channel Select for Multichannel ADC
I am using a FPGA to control a 4-channel ADC (ADC084S101) to sample four different analog voltages. In order to tell the ADC which channel to sample next, there is a control register that can be ...
1
vote
0answers
54 views
Measuring power consumption of VHDL code
I am trying to find power consumption of my vhdl code.I am going to use the power estimator in xilinx 9.2.Do the power analysis results vary in xilinx 9.2 and xilinx 14.7??
Also will xilinx provide ...
0
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0answers
35 views
How to Erase and Flash MachXo2 with FTDI and JTAG communication
I am new to Jtag, in my project i am using FTDI2232H and MachXO2-1200ZE CPLD while i am trasferring Opcode of read device ID [0xE0] i am getting Perfect device id.
here is my Device Id code
...
3
votes
1answer
45 views
HCI UART ? what's the difference with simple UART?
For now, I'm sending bytes from FPGA (verilog) to serial at 115200 bps.
I would like to send at higher speed and connect to a bluetooth module (RN42).
UART (SPP or HCI) and USB (HCI only) data ...
1
vote
1answer
76 views
AND Gate and posedge CLK ? simple question
I'm trying to do the seq system as the picture, I'm sure it's simple but I don't remember the "gate" of this.
This clock cond will be used for sending bit in ...
2
votes
0answers
72 views
Two different ways of writing the same thing but generating different behaviours in Verilog
I have a part of Verilog code that is basically trying to synthesize a flip-flop. I have been experimenting and it seems that I can come up with two ways of writing it.
The first way being :
...
3
votes
1answer
56 views
Advantage of clock enable over clock division
I have an FPGA design which uses different clocks. There is a 100 MHz reference clock provided by an oscillator. The reference clock is used in a DCM (Xilinx FPGA) to generate 3 related clocks, 100 ...
2
votes
5answers
135 views
Blocking vs Non Blocking Assignments
I have been having a really hard time understanding the difference between blocking and non-blocking assignments in Verilog. I mean, I understand the conceptual difference between the two, but I am ...
0
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1answer
39 views
vhdl - convert a signal to integer
I have looked around on SE but couldn t find anything that worked properly for me.
I am looking for a way to convert a 4 bit signal_vector to an integer. However I do calculations on signals as well. ...
-3
votes
1answer
16 views
IO pin for iCE40 Ultra [closed]
What is the maximum IO pin current (for regular pins, not for LED pins) for iCE40 Ultra FPGA?
3
votes
2answers
132 views
What method do you suggest for prototyping asynchronous circuits?
I got surprised and to a degree shocked by finding that there is no proper established tool for designing and prototyping asynchronous circuits.
I keep searching using google and other means to find ...
-2
votes
1answer
55 views
signed maximum detector vhdl [closed]
Sorry I've asked a similar question but I didn't get a answer so I posted this question
I'm currently designing a maximum detector in VHDL which is part of my homework.
The whole system consists of ...
3
votes
2answers
69 views
How to debug FPGA designs
This is supposed to be a followup to my previous question how to get a FPGA design that will definitely work on actual hardware. I have made a lot of progress since I asked the above question (thanks ...
1
vote
1answer
45 views
How to implement a Muller C-element in a LUT4 of a FPGA?
I am practicing Asynchronous circuit design, and I would like to have some simple experiments by building simple circuits using a Spartan-3 FPGA.
I am wondering how one can implement a 2-input and ...
6
votes
1answer
53 views
What is the difference between an array and a bus in Verilog?
I have been learning Verilog and Vivado at school, and I am now very confused by the usage of busses and arrays. Can anyone clarify the following?
What is the difference between an array and a bus?
...
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votes
2answers
58 views
FPGA: Reverse Engineer Design [closed]
I am looking to determine the plausibility of reverse engineering a design from an FPGA. Suppose a company fabricates their revolutionary design on FPGAs and I have managed to acquire one. My goal is ...
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0answers
35 views
VHDL - difference between concurrent statements and sequential statements [duplicate]
I'm fairly new to programming an FPGA using VHDL and I have a doubt. I understand that concurrent statements (the ones written outside the process) are executed simultaneously and sequential ...
0
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0answers
35 views
LVDS module on Ice ultra 40 FPGA from Lattice Semiconductor
I am trying to use the LVDS pin on ICE40 ultra FPGA. I have this code in VHDL:
...
0
votes
2answers
68 views
Synthesizeable D Flip flop for FPGA
Having played around with Verilog for some time now, I decided to graduate to implementing designs on Alltera CycloneIV FPGA using the Quartus suite.
Starting with a simple D flip flop, I face the ...
2
votes
2answers
69 views
Dividing numbers on an FPGA
I wrote a program for a Cyclone II FPGA that divides 2 64 bit numbers and returns if the remainder is 0 using the modulus (%) operation.
When I compiled the program with 64 bit numbers for the ...
1
vote
2answers
93 views
VGA driver not working
I am at the moment trying to make an vga driver for my FPGA, but something isn't going right, and I can't seem to find out what is going wrong...
The code is based on this code example:
Example VGA ...
2
votes
1answer
92 views
Example code to read device ID of MachXo2 with FTDI -JTAG
In my project I am working on MachX02 programming with FTDI master using JTAG functionality. I am trying to read device ID of MachX02, but not working, here is my sample code to read device ID of ...
1
vote
1answer
90 views
How to generate sound in VHDL
I'm new to FPGA and VHDL. I'm working on lab practical and for the practical we were already given file that has an I2C codec and the basics for the codec registers were already done but I found the ...
0
votes
0answers
45 views
CFI flash verilog write read
I'm trying to write a controller for an Async CFI flash in Verilog. I could read the ID but couldn't write and read 1-word data. Also tried to erase the flash before writing but didn't work.
The ...
1
vote
2answers
62 views
Different ways of using DSP slices in Spartan 6 FPGA
I am reading the Spartan 6 DSP slice user guide, and I need to use the DSP slice in a project of mine.
I stumbled upon this question, which basically suggests 3 ways of using the DSP slices
1) ...
1
vote
1answer
52 views
Illegal bus range or name for logic function for instance “instMyAdder” of type 4 Bit Adder
I am using QuartusII for designing a Four bit ripple carry adder.
I keep getting this error:
...
0
votes
2answers
43 views
Connecting Zynq boards fast and deterministic way
I'm trying to make a cluster with Zynq-7010 boards for a real-time application. One of them will be the master, and it will control eight client boards. The master board will also collect the data ...
1
vote
1answer
49 views
How to debug combinational loop warning in Xilinx ISE
I am designing a Binary to BCD converter logic circuit for implementation on Xilinx Spartan 6 FPGA's, and I have a warning during synthesis that looks like this :
...
-2
votes
1answer
49 views
Design of carry chain — Problems with clock's in design
I am trying to implement carry chain on FPGA and i want that resault from each block is written in register. Each block is 10 bit adder with following code:
...
4
votes
5answers
2k views
Counter for 20 GHz clock
I am designing time critical application where I need time resolution in order of 100 picoseconds.
I am considering to make an ring oscillator of 20 GHz and clock from ring oscillator.
Is there ...
-3
votes
0answers
37 views
How to instantiate Mig file to read and write data?
I want to write and read data for ddr2 for vertex 5 .I got instantiating file and instantiated in my main logic with inputs sys_clk_p,sys_clk_n,clk200_p,clk200_n,sys_rst_n. but still not understanding ...
0
votes
1answer
30 views
Compact multi-cycle adder for fpga: adding 1 to wide counter
I want to implement some kind of event counter in my FPGA design (Vendor-A or Vendor-X). I have several dozens of signals: half are 1-bit and other half of them is 5-bit. Signals are located in ...
2
votes
2answers
510 views
FPGA non-volatile progamming
I recently bought a Cyclone II FPGA here. I have been able to program it with a USB Blaster cable and the Altera Quartus Software. The problem is that when I disconnect power, I lose the program. ...
