The ddr3 tag has no usage guidance.
2
votes
1answer
69 views
What is the more frequent error in DDR Memory?
this is about DDR memory data corruption and not about STUCK address or data lines. If we have a good DDR with no memory stuck issues and we perform lots of writes and reads which type of error is ...
0
votes
1answer
68 views
Is it good practice to length match all traces of DDR3, or are only data traces important? [duplicate]
I am researching single board computers with the hope of designing on at the end of this, I am at the stage of DDR3, but can't find any good info on routing ddr3, regarding what traces need to be ...
3
votes
1answer
66 views
can high speed memory interfaces like GDDR5 or XDR ever become mainstream?
Given the limited memory on GPUs, I'm wondering why there are no socketed GDDR5 memory modules so that you can install more RAM.
The main challenge seems to be maintaining signal integrity since ...
1
vote
1answer
51 views
Tolerances for DDR3 trace matching?
What would be an acceptable tolerance for length matching trace, for DDR3 SDRAM?
0
votes
1answer
122 views
DDRx Memory: Memory Clock vs I/O Bus Clock?
When referring to DDR/DDR2/DDR3/DDR4 memories, I am not able to understand the difference between memory clock and I/O clock.
As per: https://en.wikipedia.org/wiki/Double_data_rate
DDR-200 - Memory ...
1
vote
0answers
48 views
GDDR Power Calculation
I'm wondering if there is any publicly available documents or research papers that cover GDDR power estimation?
Micron provides very nice documentation and calculators for DDR up to DDR4, however I ...
3
votes
2answers
271 views
Reset the configuration of FPGA without reprogramming
I am doing an experiment on Xilinx VC709 board. The experiment involves removing and plugging in the DDR3 RAM while the FPGA is running. But every time I plug back the RAM I have to reprogram the ...
1
vote
2answers
174 views
Termination resistors with DDR3, are they needed?
I'm using a DSP processor with one chip Micron DDR3 MT41J128M16JT in a project.
I read a lot about the termination resistors, but I'm still confused about if I really need those, I didn't start the ...
3
votes
1answer
123 views
What references cover DDR3 layout considerations?
I'm looking for succinct yet correct guidelines for evaluating a DDR3 memory PCB layout. I know that trace length matching, via style and back-drilling, and signal grouping all matter. I know that ...
0
votes
3answers
97 views
DDR3 Address Bus Quations
I'm new to EMIF (external memory interfaces) and I ran into kind of a dumb question about DDR3- not super important but mostly me just wondering if there's an answer I'm not thinking of. Basically I'm ...
2
votes
2answers
264 views
waveforms showing effect of trace-length matching for SHORT ddr/ddr2/ddr3 traces?
I've seen lots of waveform plots that illustrate the beneficial effect of things like on-die termination, and the effect is unmistakable. For example, see page 6 of this Micron technical note. I'm ...
1
vote
1answer
378 views
What type of memory allows for most parallel read/write operations per clock cycle in an FPGA?
If you imagine basic motion detection where you have two frames stored in memory: a previous 640x480 frame and the current 640x480 frame, what type of memory (SRAM, DRAM, SDRAM, DDR SDRAM, etc) would ...
1
vote
2answers
244 views
Series Termination DDR
I was Going through some application notes for the placement of Series termination of DDR and found it should be placed near to the processor.
But if I am not wrong termination resistor are placed to ...
0
votes
1answer
549 views
How is the DDR3 SDRAM addressing done?
In order to work on programming a DDR3 SDRAM, I was going through the JEDEC standard DDR3 SDRAM specification (link to pdf, pg 30).
I got a bit confused about the DDR3 addressing, a snapshot of which ...
1
vote
0answers
129 views
Creating Serial Pressence Detect data from discrete DDR RAM datasheet
I have a board that has soldered discrete DDR RAM chips. The datasheet for the DDR RAM chips is available to me. The DDR memory controller is programmed manually using pre-calculated values.
I have ...
2
votes
0answers
771 views
Why All DDR's (DDR, DDR2, DDR3) internal clock sets to 200MHz
If we see the DDR Upgrade technology explain below the internal clock of all DDR is set to 200 MHz.
DDR
For example,DDR-400
Efficient frequency data bus is 400 MHz
True clock rate (IO buffer ...
1
vote
1answer
111 views
Independence of the two channel architecture of LPDDR4
I'm working on a project involving LPDDR4. I've read the pertinent sections of the recently released JEDEC LPDDR4 spec. I have several questions regarding the independence of the two channel ...
1
vote
4answers
612 views
High speed memory interface between 2 FPGAs (Virtex 6)
I have a board with 2 Virtex 6 FPGAs, which are connected to each other through 64 parallel IO lines that can operate up to 400 MHz. One FPGA, let's call it B, also has 2 GB of DDR3 memory connected ...
2
votes
1answer
367 views
Sharing DDR3 memory between two sources
I have an FPGA and a powerful ARM processor both support DDR3. I am an experienced designer for smaller more embedded designs with less powerful CPUs but this is my first rodeo with a powerful ARM and ...
1
vote
2answers
1k views
Selecting different impedances then 50 ohm in DDR3
I've worked with DDR2 and DDR3 memories and usually stuck to 50 ohm impedance for traces. But i do see that SoCs and DDR2/3 memories seem to support other impedances such as 30, 60 and 150 ohms.
...
2
votes
0answers
343 views
Can I use full-size 64/72 bit DDR2/DDR3 memory module with CycloneV hardware controller of 24 + 24 bits?
I thinking of using Cyclone V FPGA and its hardware memory controller:
There is "Cyclone V FPGA Multiport Memory Controller" document from Altera:
...
2
votes
0answers
109 views
Compensating for unbalanced via count in DDR3 routing
I'm working on a DDR3 layout at 533Mhz clock speed in a balanced T configuration. I am currently unable to route the address/ctrl lines with an equal amount of vias (+1 on a limited number of lines). ...
2
votes
1answer
758 views
What is DDR software leveling?
What is DDR software leveling ?
How it is different from DDR2 and DDR3 ?
Why it is required and important ?
Is there a hardware leveling ?
I have found some explanation here about DDR3 and a ...
0
votes
1answer
116 views
Multiple DDR3 memory VTT source
I have 8 DDR3 chips connected to an FPGA (2 controllers) and two DSPs, where 4 DDR3 chips are connected to each of the processors. At this moment I have one VTT regulator TPS5120 on board, will that ...
3
votes
2answers
321 views
Using multiple DDR3 controllers on FPGA
We are designing an image processing pipeline on an FPGA which will need the use of memory interfaces at various pipeline stages. Because of the size of the memory required we decided to go with a ...
8
votes
1answer
836 views
Is there a PCB-layout related reasoning behind DDR memory package and footprint?
BGA DDR packages have a unique footprint. There are two columns of pads on both sides of the device, and an empty column in between.
Is there a reasoning behind the placement of these pads (in ...
