A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).
3
votes
2answers
364 views
Altera DE1-SoC Diagram
In this link is a description of the Altera DE1-SoC kit, and the bottom of the page shows the diagram of the SoC-FPGA chip. It shows some peripherals are connected to the FPGA and other are connected ...
0
votes
2answers
38 views
usb interface for fpga & Nios
I need some advice:
i want to connect an altera FPGA to a computer by USB interface.
i want to avoid placing an microcontroller in my board..
i want to set a nios II to "talk" to the computer
i only ...
0
votes
1answer
51 views
Quartus II - Can I include other files into a *.qsf file?
An Altera Quartus II project consists of one *.qpf and one or more *.qsf files. The qsf seems to be a TCL script like other EDA related settings and config files (e.g. xdc, sdc, ...).
Is is possible ...
1
vote
1answer
59 views
Quartus/SignalTap: Is there an equivalent to Xilinx's ICON, VIO, ILA IP-Cores in Altera's SignalTap?
Xilinx offers an Integrated Logic Analyzer (ILA) / called ChipScope. Altera's Quartus II comes with SignalTap - an equivalent solution.
As an advance user\$^1\$, I'm using ChipScope as pre-compiled ...
0
votes
2answers
164 views
Using GPIO in Altera
I'm trying to test the GPIO functionality of Altera (DE1, Cyclone II) with this simple program.
If the GPIO_0[0] gets a high (1) signal, LEDG[0] will light up. If it receives a low (0) signal, ...
3
votes
2answers
521 views
Clock domain crossing timing constraints for Altera
I have a slight problem with my clock domain crossing timing constraints.
I have two clock groups
set_clock_groups -asynchronous -group {clk_A} -group {clk_B}
...
0
votes
0answers
20 views
SystemVerilog interface blocks and Altera Quartus Design Partitions
It appears that Quartus (including the latest v15.0) does not look at modports when determining the direction of the ports in SystemVerilog interface blocks.
The fitter complaints that the design ...
0
votes
1answer
48 views
Help with resolving warning “inferring latch(es) for signal or variable ”..“, which holds its previous value in one or more paths through the process”
Below is the code for my branch unit implementation. This unit calculates the jump destination address and writes it into the PC register.
There are a few different types of jumps, etc, standard ...
3
votes
1answer
110 views
CDC Synchonisation primitives for an Altera FPGA
I am working on my first non-trival FPGA design and finally have a need for Clock Domain Crossing (CDC).
There are multiple resources (amongst others) which discuss various architectures for CDC and ...
0
votes
0answers
35 views
Altera Megafunction generics
I am using the Altera Megafunction LPM_ROM in one of my designs using the block diagram editor in Quartus. I want the ROM to have a configurable initialization file.
For example for my component X ...
3
votes
1answer
125 views
Altera's DRAM Controller with UniPHY
I am trying to port a design from Xilinx to Altera, and I have issues with the DRAM controller IP (for a Cyclone-V and a LPDDR2 mem).
I have managed to generate the IP, but I don't understand which ...
-1
votes
1answer
172 views
Simulating IP core (i.e ALT_FP_DIV) on Altera modelSim gives “z” (high impedance) as output
I'm trying to simulate (functional Test) a project that contains both my own codes and some instances of Altera Floating Point IP Core generated using MegaWizard on ModelSim.
All the instantiated IP ...
3
votes
2answers
1k views
Verilog FIR filter using FPGA
I am implementing an FIR filter in Verilog, using the DE2 board. For some reason the output out of the speakers is full of static, although it does appear to filter out some frequencies. Here is the ...
0
votes
1answer
31 views
Nesting entities in VHDL (Altera Quartus)
I want to ask a question. I'm trying to simulate a cpu. I did my schema and basically there are two logical parts of the CPU.
The first part is composed of a FIFO buffer, Cache memory for ...
1
vote
1answer
75 views
Benefits of using Altera IP in FPGA designs?
I've just started using Quartus to synthesize a VHDL design that I created a while ago. Inside of this design are things like DFFs, decoders, etc. I noticed that Altera has IP of its own with the same ...
0
votes
2answers
54 views
How are FPGA's configured when operating independently?
I have a DE0 Altera board with a Cyclone III FPGA from my VHDL class, and I want to learn how to use it in an independent device. Right now I have a Raspberry Pi and wanted to try playing with using ...
0
votes
1answer
47 views
Does the altera ROM megafunction have a startup delay?
I'm trying to make a very simple single cycle CPU in VHDL. My machine code is stored in a ROM that was made by the Altera MegaWizard. The first word that is stored in this ROM is 0x1111. After writing ...
0
votes
3answers
212 views
SignalTap II: OR trigger conditions, instead of AND
I'm using the Altera SignalTap II that comes with Quartus II. As far as I understand, each pin can be assigned a trigger condition. It seems that acquisition only stops when all the trigger conditions ...
0
votes
1answer
62 views
VHDL code works well in ModelSim and strange behavior in Altera FPGA
I'm trying to understand a strange (for me) behavior of a simple VHDL code. I have realized a stupid code that works well in ModelSim and doesn't work in a real FPGA (Altera MAX 10).
...
0
votes
2answers
218 views
How to read firmware from Altera's FPGA (Cyclone IV) with USB Blaster?
I'm starting to investigate Altera's Cyclone IV FPGA to use in my projects. Now I borrowed from neighboring company a real device with USB Baster Rev.C. I'd try to use one instead of evaluation board ...
0
votes
0answers
58 views
OR1K on DE0-Nano
I seem to be having difficulty finding much information on implementing the OpenRisc architecture onto the DE0-nano with support for linux. I found one particular article on the official site from an ...
-2
votes
1answer
65 views
Write an I2C code for Cyclone 2 architecture
I really need to I2C interface my FPGA with some slave device. I figured I could use the audio codec in my FPGA as a slave.I have gone through some codes from the internet for I2C. But I do not get ...
0
votes
0answers
42 views
How to compile .qsys file in modelsim?
My project contains both .qsys and .vhd files. I want to simulate my project using modelsim before programing to FPGA. For ModelSim to simulate first all files should be compiled.
From what I know ...
0
votes
0answers
105 views
Having FPGA to output sound on “line out” pin using verilog
I am trying to write a verilog code for FPGA which will output sound from the embedded "line out" pin. I use Quartus II and Altera DE1.
I am new to hardware programming, therefore it just takes too ...
1
vote
1answer
251 views
Memory logic array blocks VS M20K
I am looking at the Altera Stratix V overview Table 1. In it, they distinguish two types of memories:
M20K memory blocks
Memory logic array blocks (MLAB)
What ...
0
votes
0answers
44 views
Resistance or impedance offered by GPIO pins and SMA external clock pin in cyclone 2
I tried connecting a square wave from a signal generator as an external clock through the SMA pin. But I need to know the impedance offered by the SMA pin. What is it and how o find it? Besides the ...
0
votes
3answers
209 views
sine wave in FPGA
I am supposed to generate a sine wave in cyclone 2 altera? I get that I have to store the values in LUT or some memory. I think cyclone 2 uses a 4 input LUT. I am not sure how I should go on with the ...
1
vote
3answers
167 views
PCI-Express and FPGA Development Boards
I'm interested in using some high-performance FPGA development boards, but it seems like most of the high-end, modern options from both Xilinx (Digilent) and Altera (Terasic) seem to be PCIe-based ...
0
votes
0answers
88 views
How the change the frequency of a clock in Quartus II?
I have a clock in VHDL:
...
process(clock)
begin
if rising_edge(clock) then
...
When I check the timequest analyzer, it sets this clock to a default 1 GHz ...
-1
votes
1answer
72 views
Altera Clock + PLL
I am using an Altera devkit from terasic, DE0-CV. I am also new to the FPGA business.
How to connect the onboard clock to the FPGA and use it with my design?
As the clock is a 50 MHz one, surely I ...
2
votes
1answer
70 views
Using the ROM megafunction in VHDL code
I have created a ROM megafunction using the MegaWizard plug-in Manager. This created a new file which I named rom.vhd.
My code:
...
0
votes
1answer
25 views
Node assigned to IOBANK
I'm working with an Altera FPGA. In the Pin Planner there is a choice in the combo box for a 1-bit inout node to be connected to an "IOBANK_n" (under "Location" row). I was expecting only "PIN_nn" are ...
0
votes
3answers
253 views
0
votes
2answers
161 views
FPGA SPI slave not working well
I'm tring to integrate a SPI Slave in VHDL (opencores)
http://opencores.org/project,spi_master_slave
the idea is to interface a Microcontroller and an FPGA
I'm Using Quartus..
more info:
...
4
votes
3answers
1k views
FPGA encoder counter running away randomly
I am programming an Altera FPGA using Quartus II v9.0 to count encoder pulses and output that count to an external LabVIEW program (see diagram below). I was able to debug one issue with my code ...
2
votes
1answer
141 views
Why does this Verilog code produce no output on my FPGA?
I am trying to learn Verilog on my own using the DE1-Soc and the Altera university program labs. I am on the very first lab and trying to make a 4 bit-wide two input multiplexer. I wrote this verilog ...
0
votes
0answers
85 views
How to output audio using an altera DE0 FPGA?
I am working on a project that involves realtime image processing using altera DE0 fpga board. Due to the nature of the project I am also really interested in including audio output. However according ...
1
vote
2answers
248 views
Reading ADC using Altera DE2 Board (Beginner)
Question:
Would it be possible and feasible for a beginner to use Verilog HDL and an Altera DE2 board to read input from a weight sensor's HX711 ADC (see below), and if so:
What kind of data am I ...
0
votes
1answer
53 views
Why build errors when connecting timers in Quartus ii?
I use the Nios 2 IDE from Altera with the Altera DE2. I add a file Functions.c with code that needs a timer e.g.
...
-1
votes
1answer
51 views
How to constrain fitter to assign signals to specific LE input in Quartus II?
I have noticed that the time delay through a combinatorial cell in an LE can depend significantly (up to .1 ns on my DE-0 Nano Cyclone IV board) on which input, A thru D, the input is assigned to. To ...
1
vote
1answer
936 views
How to install Altera USB master driver for Windows 8 (64 bit)?
I am trying to connect Altera Stratix 4 board with my PC in which Quartus 11.0 is per-installed. But my PC is not detecting USB JTAG connection from the board.
What I am guessing is that, this ...
0
votes
1answer
121 views
Can DE2-115 handle more than 3.3V on its GPIO
In my current project I want to connect some logic to Altera DE2-115 using 40-pin exapnsion header (JP5). Unfortunately, I can't ...
0
votes
1answer
149 views
Interfacing DDS with FPGA
I'm trying to use an FPGA (Altera Deo-Nano) to send data to a DDS (AD9910) using the parallel ports of the DDS. I am using the GPIO headers of the FPGA. I have only connected the parallel input pins ...
0
votes
1answer
88 views
reuse Cyclone IV fpga Pasive serial configuration pin for SPI
Can i reuse pins DATA0 & DCLK in my application as FPGA SPI interface after configuration (PS) has been completed ?
This are the dual purpose pin options:
if i set "use as Regular I/O" , i ...
0
votes
2answers
119 views
Code to add two 4bit numbers in verilog doesn't work
I have a code that adds two 4 bit numbers; unfortunately it is not working for every case even though the formulas are really simple and I don't find the problem...
...
-4
votes
1answer
128 views
Is it technically feasible to design a microchip that won't fail foreign characters? [closed]
I used to work as web developer and did the same part of the project for several decades: Making sure that our Scandinavian characters åäöÅÄÖ... will work. It was feasible and it did work, basically ...
-1
votes
1answer
31 views
What's the order of the array generated by Verilog? Syntax
What is the correct interpretation between these two lines:
wire[2:0] w = SW[17:15] = {SW[17], SW[16], SW[15]}
wire[2:0] w = SW[17:15] = {SW[15], SW[16], SW[17]}
When I call w[0] will I get SW[15] ...
2
votes
1answer
209 views
How do for loops work in verilog? Why can't I achieve what I want?
This is my code for a simple 2-1 8 bit multiplexor, where SW[17] is my selector.
If it is on, show Y = SW[15:8], if it is off, ...
0
votes
1answer
131 views
Extracting a sub array from an array of switches with Verilog?
I am working with a Cyclone board. A basic code to assign every switch to the red leds is:
...
1
vote
1answer
75 views
ALU once compiled giving errors of missing source signal?
This is ALU, not sure whether if it is all properly connected but all blocks are the correct ones. This has 3 4 bit latch registers, 5 2:1 ultiplexers, 4 4 bit adders. Can anyone help me?
The problems ...
