Questions tagged [questasim]
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8
questions
1
vote
1answer
86 views
Error with Assert statement in Verilog
I have the following assert statement in a for loop, which is within a generate block:
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0
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2answers
182 views
Is there a way to define enumeration for certain signals after simulation?
I have run some verilog simulations in questa simulator and while viewing the waveforms i see that it would have been easier for me to debug the signals had there been some enums defined for them (To ...
0
votes
1answer
1k views
VHDL: reading integers from a text file, storing them in array, and writing in text format again
In a certain simulation testbench using questasim, I am trying to read the files with integers numbers which looks like,
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0
votes
1answer
141 views
A question about randomization in verilog
I am now working on a verilog testbench file and I want to get a random value in my code, but I have found that Questa Sim uses the same seed again and again. I have read through $random in Verilog ...
0
votes
1answer
171 views
Is there a way to suppress the output when compiling multiple vhd files except for errors?
I have a compilation script I run before simulating on QuestaSim 10.7:
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0
votes
1answer
2k views
VHDL: Non-locally static choice warning
I have the following code:
constant HALF_RANGE: unsigned(RANGE_WIDTH-1 downto 0) := (RANGE_WIDTH-1 => '1', others=>'0');
where RANGE_WIDTH is a generic of ...
0
votes
1answer
318 views
“Numeric value exceeds 32-bit capacity” error in QuestaSim
In the testbench for a SystemVerilog module, I have the following array declaration and initialization:
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1
vote
1answer
2k views
ModelSim: Why can't I see generics in simulation?
When I start simulation, I can see signals and ports in the objects window for what I have selected in the Sim window. Besides this, I can see processes for the same thing in the processes window. ...
