Newest &#39;synthesis&#39; Questions

0

votes

0answers

44 views

Procedures or structural architecture - which is preferable for synthesis in VHDL?

I'm writing VHDL code which I would like to implement on an FPGA. Currently I have written separate architectures for adders, multipliers etc and combined them all using a structural architecture in ...

asked Apr 7 at 10:05

ayerhs7

142

1

vote

1answer

36 views

Synthesisable alternative to the wait statement in VHDL

I'm writing VHDL code for a filter which I want to implement on a Spartan 6 FPGA. When I tried running a testbench for my code, one of the processes entered an infinite loop, so I added a wait ...

fpga vhdl synthesis

asked Apr 7 at 7:47

ayerhs7

142

2

votes

0answers

31 views

How to specify a minimum clock to output time in output timing constrain?

In a design, an external clock pin triggers a flip-flop, where the output goes to an external data pin. Using Xilinx ISE, how can I specify a timing constrain, so the output should be held for some ...

fpga xilinx synthesis constraints

asked Mar 30 at 12:49

EquipDev

1135

0

votes

2answers

57 views

Assigning x in verilog

Assume there exists a 1 bit data output port and a 1 bit dataValid output port for a module. Is it OK to assign 1'dx to the data output when dataValid is assigned 0? Will this create synthesis issues? ...

verilog synthesis system-verilog asic

asked Mar 28 at 16:35

Revanth Kamaraj

42

1

vote

1answer

25 views

how do you know the each parameter values of SDC at the first time?

when we do synthesis with SDC. we should be used with SDC. But I want to know what if you are in situation where the synthesis of yours is the first time, also the company does not even did synthesis ...

synthesis asic soc

asked Mar 28 at 5:28

nashile

134

1

vote

1answer

25 views

non static error in Precision RTL

I'm writing a VHDL code for an integer to float converter using variables. I have simulated it and the results match expectations. However, when looking to compile and synthesize using Precision RTL ...

vhdl synthesis

asked Mar 25 at 14:45

alekt

83

2

votes

1answer

41 views

SDC constraints for two flop sychronizer

I have doubt, What should be proper SDC constraint for CDC module, i.e., two flop synchronizer. between "dat driving by aclk to ...

synthesis vlsi timing-analysis chip-design constraints

asked Mar 18 at 5:01

Prakash Darji

3859

2

votes

0answers

76 views

Two different ways of writing the same thing but generating different behaviours in Verilog

I have a part of Verilog code that is basically trying to synthesize a flip-flop. I have been experimenting and it seems that I can come up with two ways of writing it. The first way being : ...

digital-logic fpga verilog simulation synthesis

asked Mar 17 at 4:16

ironstein

998

2

votes

5answers

140 views

Blocking vs Non Blocking Assignments

I have been having a really hard time understanding the difference between blocking and non-blocking assignments in Verilog. I mean, I understand the conceptual difference between the two, but I am ...

fpga verilog synthesis system-verilog

asked Mar 15 at 16:00

ironstein

998

6

votes

4answers

958 views

How to get a FPGA design that will definitely work on actual hardware

I have just started learning digital logic design with FPGA's, and have been building a lot of projects. Most of the times (since I am kind of a noob), I have a design that simulates perfectly ...

fpga design xilinx synthesis

asked Mar 2 at 4:44

ironstein

998

0

votes

0answers

27 views

How to borrow time in STA?

Now I'm trying to study about time borrow as refer to here: "Time Borrowing": Static Timing Analysis (STA) basic (Part 2). Especially, I'm looking at this: How to get time and how to get this not ...

synthesis

asked Feb 25 at 10:09

gagaga

11

1

vote

2answers

37 views

In Verilog Synthesis, Creating several Instantiation of a Module is the same than instantiate several modules with same content?

I wonder if there is a difference between creating several instantiation of a single module and to instantiate different modules (with identical hardware code) only one time. For example, I want to ...

verilog synthesis

asked Feb 13 at 10:55

sujeto1

415

-2

votes

1answer

66 views

Explanation of how to create circuit from transfer function

So I'm in this lab course that must be taken concurrently with the main upper div circuits class, but we were assigned a lab that our professor did not explain and that the lab manual does not ...

synthesis function transfer

asked Feb 6 at 7:19

jonnyd42

716

-1

votes

1answer

106 views

How to properly describe a Math Equation in Verilog to be synthesizable?

I have not been able to find a book or information in internet, about the correct way to describe a Math Equation in Verilog. With the correct way I mean for example, how to analyze the equation and ...

fpga verilog math synthesis

asked Feb 4 at 13:09

sujeto1

415

2

votes

0answers

23 views

How to define a false path using design entities

I'm trying to do a timing analysis on a design I wrote in VHDL. The design looks like this: And the mux's are only activated in a way that the path is either: in -> circuit1 -> circuit2 -> out in ...

synthesis vivado

asked Jan 20 at 15:21

Michael Fivez

111

1

vote

1answer

80 views

How can I constrain an imported netlist in Vivado?

I have a pre-compiled netlist (created by Xilinx ISE 14.7), which is imported into Vivado 2015.4 and used in synthesis to assemble my complete design. Vivado reports unconstrained paths for the ...

fpga xilinx synthesis vivado timing-analysis

asked Jan 16 at 0:27

Paebbels

2,2451323

0

votes

1answer

53 views

How is the difference between sdf back annotation and spf back annotation?

I'm a rtl engineer. I'm confused between the difference of sdf and spf back annotation. As I know sdf came from STA( PT) and SPF came from STAR-RC. So In my experiance, the sdf used to timing close ...

synthesis asic

asked Dec 31 '15 at 1:30

bural

296

2

votes

0answers

39 views

Does sequential clock gating useful? [closed]

I know there is clock gating method that xor-ing the input and output of FF, and use that signal as clock enable. (figure 1, i'll call it xor-ing from now) I'm now studying sequential clock gating. I ...

clock synthesis

asked Dec 20 '15 at 17:29

user2493934

141

2

votes

2answers

136 views

Can a flip flop possibly work at over 800MHz? [closed]

As I know, the setup time is at least required time for data to become stable at the input of a FF before the sensitive clock edge. Hold time is the required time for data to remain stable after the ...

synthesis rtl process

asked Dec 15 '15 at 2:21

bural

296

2

votes

0answers

47 views

Xilinx unconstrained path analysis

I'm using Xilinx ISE 14.7 to implement my design but I have some doubts about how to read the constraint interaction report (.tsi) generated during the Post Place&Route Static Timing Analysis. ...

fpga xilinx synthesis

asked Dec 1 '15 at 19:46

Alessandro

111

1

vote

0answers

18 views

Synplify Pro- Identify debugger problem

I'm using synplify pro from Synopsys for Microsemi IGLOO FPGA synthesis. and I want to debug the FPGA using Identify debugger, but it cann't connect to the JTAG port and gives me this error when doing ...

fpga debugging synthesis libero

asked Nov 24 '15 at 14:44

ELEgeek

294

2

votes

0answers

144 views

Vivado HLS: Is it Xilinx specific?

I've been using Vivado HLS (High-Level Synthesis) for the last months and making designs for a Xilinx's ZedBoard. Now I will probably have to work with a FPGA from another vendor and I don't know if ...

fpga xilinx synthesis

asked Nov 12 '15 at 14:43

João Pereira

978

1

vote

1answer

83 views

Some pointers on how to begin VHDL writing

I'm currently doing some tutorials and reading some books on how to write VHDL. As I'm curious and learn better with hands-on tutorials I'm going to start implementing my projects that will serve me ...

fpga vhdl simulation synthesis

asked Nov 10 '15 at 16:31

João Pereira

978

0

votes

1answer

72 views

Synthesis tool free-source [closed]

I'm currently learning VHDL and to simulate the code that I write I found out GHDL (open-source), which I haven't tried yet but I think does what it needs to be done. In order to synthesize the VDHL ...

fpga vhdl simulation synthesis

asked Nov 4 '15 at 13:33

João Pereira

978

1

vote

1answer

108 views

loop synthesis vhdl

Suppose we have an iterative algorithm like: r(j) := f(r(j-1)) r(0) := value And that vhdl i implemened a process for such algorithms (assuming a bit of ...

vhdl synthesis process

asked Oct 12 '15 at 13:53

lukkio

24218

0

votes

1answer

39 views

Product-of-Sums Synthesis

Alright, have another one which the solutions manual is vague on. I have to reduce \$f =(x1+x3+x4)(x1+x2'+x3)(x1+x2'+x3'+x4)\$. Right in the first step, though, the solution does something I don't ...

digital-logic synthesis

asked Oct 11 '15 at 22:09

PoGaMi

758

1

vote

2answers

111 views

Constant value required for VHDL array indexing?

I basically have a line like this in a vhdl code. ...

vhdl signal synthesis

asked Oct 9 '15 at 9:04

lukkio

24218

1

vote

1answer

43 views

How to concatenate unsized parameters

My verilog module is instantiated in a VHDL top entity. I want to pass integer design-time configurations to the verilog module. These are the initial configurations that should appear at reset. ...

verilog synthesis

asked Oct 7 '15 at 14:49

Tarek Eldeeb

1083

1

vote

0answers

61 views

Operator synthesis VHDL, numeric_std.vhd

if i include the library numeric_std.vhd (the implementation is here https://standards.ieee.org/downloads/1076/1076.2-1996/numeric_std-body.vhdl) you can see that the operator *,+ (as instance are ...

vhdl computer-architecture synthesis compiler optimization

asked Sep 17 '15 at 13:36

lukkio

24218

1

vote

1answer

74 views

removing inout from port arrays

This question is in the context of using verilog/systemverilog for synthesizable RTL. I have some vector signals that are going across module boundaries that are currently defined as inout ports. The ...

digital-logic verilog synthesis rtl

asked Sep 12 '15 at 19:01

mattgately

1616

3

votes

1answer

151 views

VHDL functions with generic or “run time variable”, synthesis issues

I have been thinking about functions in VHDL. If we have a function we could have both a function where we pass a "generic" (i.e. a fixed parameter known at compilation time) and a variable/signal ...

vhdl synthesis function

asked Sep 10 '15 at 12:00

lukkio

24218

0

votes

1answer

316 views

Xilinx ISE Synthesis taking too long

I just finished to write a pretty complete design on ISE 14.7 targetting a Virtex7 device. The behavioural simulation (on Isim) takes a while but works perfectly. Therefore, I tried to move to the ...

xilinx synthesis ise optimization virtex-series-fpga

asked Sep 6 '15 at 17:30

asonnino

264

1

vote

0answers

31 views

Synthesis error when using “-opt_mode area” in Xilinx XST

I am experiencing fatal errors when synthesising my design with Xilinx XST 14.7 and the -opt_mode option set to area. With ...

xilinx synthesis ise

asked Aug 27 '15 at 10:40

damage

444311

1

vote

1answer

78 views

Nonlinear increase in logic utilization for FPGA design

I am creating a design using the Altera Stratix V GX-series FPGA. For host device communication we are using the PCIe x8 interface. The interface itself takes up 3,058 ALMs (out of available ...

digital-logic fpga synthesis

asked Aug 4 '15 at 16:40

Ted X

333

2

votes

2answers

240 views

How to understand the timing report after synthesis?

After synthesis of my verilog code. I am getting the below timing report. I think it showing any mistake in my code. Timing Summary: Speed Grade: -2 Minimum period: 2.334ns ...

verilog xilinx synthesis

asked Jul 26 '15 at 7:12

Shine_flower

717

1

vote

1answer

66 views

how to interpret the RTL report after synthesis in Xilinx?

I did verilog code of a circuit. It was simulating well and giving output correct after Simulation. Now i did synthesis, the RTL schematic after synthesis showing some green and red box. Is it ...

xilinx synthesis rtl virtex-series-fpga

asked Jul 19 '15 at 11:07

Shine_flower

717

0

votes

2answers

409 views

How to find high fanout nets?

In the timing report of a synthesis with Synopsys VCS, a warning states: Warning: Design contains 8 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these ...

verilog synthesis asic timing-analysis rtl

asked Jul 8 '15 at 7:25

Moberg

1012

0

votes

1answer

36 views

data bus power consumption

In a design I have, I am using a memory arb (receiving mem requests from two masters) What are the pros and cons for each of the follwing: use a mux for the read data of each master, so that if the ...

vlsi synthesis asic timing-analysis

asked Jul 6 '15 at 8:08

tom

1

vote

1answer

159 views

This design does not fit into the number of slices available in this device

Below is the device utilization summary for the design(Zynq 7010) and the use of Slice LUTs exceeds the availabile number. Previously it was 82% and now it exceeds after adding a block of checksum ...

xilinx synthesis planahead

asked Jul 1 '15 at 13:35

Pradeep S

1166

1

vote

1answer

267 views

getting started fpga video processing? [closed]

Hi i am a electrical engineering student first year since we study only microcontrollers and processors I have decided to learn more about fpga (I have a little experience with spartan 3e vhdl) . My ...

fpga dsp signal-processing synthesis

asked Apr 22 '15 at 12:45

user2686117

61

0

votes

1answer

121 views

searching in memory at verilog

I need to make a module which responsible to search overall memory to find a specific value and return the address location, but I have the following error after do Synthesize in Xilinx. ...

verilog memory ram synthesis ise

asked Apr 10 '15 at 14:40

Hanaa

1

0

votes

1answer

47 views

VHDL synthesizing a module doesn't work, but simulating it does. Error: Bad synchronouse description

I am wondering why synthesizing this code doesn't work, but simulating does. ONLY WHEN TRYING TO SYNTHESIZE I get the following error: Signal sig_enable cannot be synthesized, bad synchronous ...

fpga vhdl synthesis

asked Apr 5 '15 at 18:47

Calin

195213

2

votes

3answers

427 views

Thought Process on Designing Circuits

I'm currently in my second year of computer engineering. I've taken circuit analysis courses and have a good general understanding of components, and a little bit of digital design, however, I'm very ...

components analysis synthesis

asked Mar 29 '15 at 22:45

Scooted

132

1

vote

1answer

176 views

Why does Xilinx Translate for Virtex-6 not know IOSTANDARD LVDS?

I'm using several Xilinx FPGAs and boards from Spartan3E up to KC705/VC707 and I'm very familiar with UCF files, but there is one question that bothers me... Why does translate for Virtex-6 not know ...

xilinx synthesis ise virtex-series-fpga ucf

asked Mar 17 '15 at 23:31

Paebbels

2,2451323

1

vote

2answers

98 views

How to best synthesize a systolic circuit on FPGA?

I am developing a parameterized systolic circuit in VHDL, using generics. It exhibits regularity in 2 dimensions. I am about to synthesize it on Xilinx FPGA. I suspect it is worth informing the ...

fpga vhdl xilinx synthesis ise

asked Nov 16 '14 at 11:54

JCLL

244211

1

vote

1answer

480 views

Finding Critical Path of Combinational Logic

I have a combinational circuit and I would like to find its critical path in design compiler. Essentially, I want to find out by how much the combinational logic will reduce the maximum clock ...

digital-logic verilog synthesis

asked Nov 14 '14 at 0:05

Mowgli

1215

2

votes

1answer

230 views

Why two Xilinx scripts with different bitgen options yield correct and incorrect behaviors?

I am really puzzled by a FPGA synthesis problem on Xilinx ISE. Precisely, it took me a long hour to discover why a same RTL design (set of VHDL files) works like a charm on a board using a synthesis ...

fpga xilinx synthesis

asked Oct 10 '14 at 12:21

JCLL

244211

1

vote

1answer

112 views

In VHDL what is a data operator type “variable” when it is translated to circuit? [duplicate]

VHDL code is finally converted into hardware equivalent when it is synthesized. What happens to data operator type "variable" when it is synthesized?

vhdl xilinx synthesis data-operator

asked Jul 25 '14 at 4:54

tollin

1,10911030

3

votes

1answer

283 views

How do you constrain input delay for a multidimenionsal input vector?

I am defining SDC input constraints for synthesis of a small module that is part of a larger ASIC design. I plan to run the module through synthesis using Synopsys tools. A few of the inputs to this ...

synthesis asic constraints chip-design

asked Jul 2 '14 at 0:33

Matt B.

182

1

vote

1answer

125 views

Boolean Network Simplification using Satisfiability Don't care Conditions

I couldn't really understand how SDC conditions are applied to minimize the following Boolean Network from Giovanni De Micheli's slide I am studying. Given: $$x=a'+b$$ $$y=abx + a'cx$$ Minimize ...

synthesis optimization

asked Jun 25 '14 at 23:20

mill

63

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