Newest &#39;xilinx&#39; Questions

6

votes

2answers

134 views

Do I need to reset my FPGA design after startup?

I usually initialize state registers of my FSMs by specifying an initial value in my VHDL code, so that, I do not require a reset pulse after startup of the configured FPGA. The following example ...

asked Apr 12 at 14:17

Martin Zabel

1,3621117

-1

votes

1answer

26 views

How to create .VCD file or Simulation activity file of verilog code?

I have Verilog's code. It is simulated correctly and synthesize too. I wanted to write.VCD(value change dumped) file. I got from internet few command to generate VCD file as given below: ...

verilog xilinx

asked Apr 11 at 7:07

RO.BST

155

1

vote

1answer

69 views

Generating video with ZYNQ, using IP block design?

I am trying to implement a video streamer on Digilent ZYBO board that has Xilinx ZYNQ 7010. By the way, reason of this thing is to test the quality of an encoder board. What I want is to: Generate a ...

fpga xilinx video vivado dma

asked Apr 7 at 16:16

ddyn

297

0

votes

0answers

53 views

7 Series FPGA - Displaying Output From A Signal

...

fpga vhdl simulation xilinx

asked Apr 6 at 21:58

cong6032

62

3

votes

1answer

45 views

Xilinx ISE warns that a signal is trimmed since it has a constant value of 0, but the signal is used within my code

I have created the following VHDL module, which is used as an up/down counter. ...

fpga vhdl xilinx

asked Apr 6 at 12:00

Jazula

182

0

votes

1answer

38 views

TX/RX pins on Xilinx Zynq

I have been using a Spartan 6 where the TX/RX pins are multiplexed with the IO pins, I can't find any dedicated TX/RX pins on the Xilinx Zynq Soc, is it a Xilinx thing to multiplex TX/RX with IO ...

xilinx

asked Apr 5 at 12:49

Alex

927

2

votes

0answers

31 views

How to specify a minimum clock to output time in output timing constrain?

In a design, an external clock pin triggers a flip-flop, where the output goes to an external data pin. Using Xilinx ISE, how can I specify a timing constrain, so the output should be held for some ...

fpga xilinx synthesis constraints

asked Mar 30 at 12:49

EquipDev

1135

-2

votes

0answers

19 views

Design 2x1 multiplexer using VHDL [duplicate]

I need to design frequency for a 2x1 multiplexer using HDL for my project. The description is: If select = 0, output = input 1 (10kHz) If select = 1, output = input 2 (100kHz) The problem is, I ...

fpga vhdl xilinx multiplexer

asked Mar 30 at 4:38

jaiko

43

0

votes

2answers

36 views

How to generate IP cores with access to hardware in vivado

I am looking for some guide on how create an IP-Core in Vivado which make integrate the hardware. I want to create a IP-Core which should act as an driver for VGA port. The problem is how to create it ...

vhdl xilinx vga vivado

asked Mar 28 at 7:09

dfh

94

4

votes

2answers

88 views

Dual port RAM on Altera and Xilinx FPGA

I have always managed to synthesis a 256 x 32 bits dual-port RAM (not true dual port RAM) in Xilinx ISE with just 1 x 18K BRAM. The example code from here was used: ...

fpga vhdl xilinx altera ram

asked Mar 28 at 7:06

John

234

1

vote

1answer

77 views

FPGA Frequency Divider

I need to design frequency divider from 50MHz to 200Hz using FPGA. I'm using Xilinx and the language that I used is VHDL language. I got stuck because I can't get the output. So, anyone can help me? ...

fpga pwm vhdl xilinx frequency-divider

asked Mar 26 at 14:59

jaiko

43

0

votes

0answers

28 views

Failure: (vsim-3808) Incompatible modes for port

I am attempting use modelsim to simulate a peak detector and am having trouble with the simulation of the handshaking protocol between two modules: dataGen and dataConsume. I am certain that the code ...

fpga vhdl xilinx modelsim code

asked Mar 24 at 15:30

bikerclown

1

vote

0answers

59 views

Measuring power consumption of VHDL code

I am trying to find power consumption of my vhdl code.I am going to use the power estimator in xilinx 9.2.Do the power analysis results vary in xilinx 9.2 and xilinx 14.7?? Also will xilinx provide ...

power fpga xilinx

asked Mar 22 at 14:02

Rocker

61

1

vote

1answer

98 views

Simple binary adder works only partially

LATER EDIT: 1. I've also investigated visually the Kintex7 device after implementation (i.e. interconnections, etc.) and everything looks OK - no connections that would indicate things would not be ...

vhdl xilinx adder pcie vivado

asked Mar 17 at 22:57

BogdanSorlea

397

3

votes

2answers

70 views

How to debug FPGA designs

This is supposed to be a followup to my previous question how to get a FPGA design that will definitely work on actual hardware. I have made a lot of progress since I asked the above question (thanks ...

fpga simulation xilinx debugging

asked Mar 12 at 18:43

ironstein

998

1

vote

1answer

27 views

What is traffic generator (while using Xilinx Memory Interface Generator)

I am trying to use the Memory controller Block in my Xilinx Spartan 6 FPGA to set up an interface with LPDDR memory. I read the MCB User guide, and I am quite clear about how it works, and how I would ...

memory xilinx ddr

asked Mar 7 at 17:20

ironstein

998

1

vote

2answers

74 views

Different ways of using DSP slices in Spartan 6 FPGA

I am reading the Spartan 6 DSP slice user guide, and I need to use the DSP slice in a project of mine. I stumbled upon this question, which basically suggests 3 ways of using the DSP slices 1) ...

fpga xilinx dsp hdl

asked Mar 6 at 3:26

ironstein

998

0

votes

2answers

44 views

Connecting Zynq boards fast and deterministic way

I'm trying to make a cluster with Zynq-7010 boards for a real-time application. One of them will be the master, and it will control eight client boards. The master board will also collect the data ...

fpga xilinx microprocessor digital-communications network

asked Mar 4 at 23:23

zontragon

1688

3

votes

1answer

45 views

Modelsim - Weird verification problem with DDR and Xilinx UNISIM

I am doing verification of VHDL component using OVM and ran into serious problems. I have found that problem is in one specific component and created environment specifically for it. It's a RGMII to ...

vhdl xilinx system-verilog modelsim verification

asked Mar 3 at 23:25

David Novák

265

1

vote

1answer

52 views

How to debug combinational loop warning in Xilinx ISE

I am designing a Binary to BCD converter logic circuit for implementation on Xilinx Spartan 6 FPGA's, and I have a warning during synthesis that looks like this : ...

fpga schematics xilinx rtl combinationalcircuits

asked Mar 3 at 20:37

ironstein

998

0

votes

0answers

43 views

Error in use of COMPONENT (VHDL)

I've designed a simple adder using "FOR GENERATE" in VHDL. It returns this error: " main is not an architecture body for full_adder in library WORK." I've defined a COMPONENT named FA to be a ...

vhdl xilinx ise

asked Mar 2 at 16:22

SMA.D

10210

6

votes

4answers

958 views

How to get a FPGA design that will definitely work on actual hardware

I have just started learning digital logic design with FPGA's, and have been building a lot of projects. Most of the times (since I am kind of a noob), I have a design that simulates perfectly ...

fpga design xilinx synthesis

asked Mar 2 at 4:44

ironstein

998

0

votes

2answers

45 views

Zynq - Configuring SPI clock to idle high

I am trying to use the SPI0 component of a Zynq XC7Z010 to read data from a 12-bit rotary encoder which uses an SSI protocol. I have a small example project set up in Vivado which enables the SPI0 ...

fpga spi xilinx vivado

asked Mar 1 at 10:29

Tusike

31

1

vote

2answers

89 views

how to understand xilinx RTL schematics [closed]

I am learning digital logic design with FPGA's, and I am using the Xilinx Spartan6 FPGA. I am able to successfully able to simulate my design correctly, but the design does not work properly, when I ...

fpga xilinx rtl

asked Mar 1 at 4:34

ironstein

998

1

vote

1answer

52 views

Automated multiplexer in vhdl

I'd like to make a MUXer who switches between 2 signals let's say A and B. Signal A and B also generate both interrupts. The MUXer counts the interrupts and for example after n-interrupts of A, the ...

fpga vhdl xilinx state-machines

asked Feb 20 at 12:08

user3488736

103

-5

votes

1answer

26 views

verilog code to perform {w=(3*(p+t-1))/t} with look up taples

I want verilog code to perform {w=(p+t-1)/t} with look up taples . The lookup table is to be realized as a ROM where: p is 3 bits t is 2 bits (and not equal to 0)

digital-logic verilog xilinx

asked Feb 5 at 22:07

ahmed salman

23

0

votes

1answer

57 views

designing a state machine to detect a certain bit

So, I need to create a state machine (mealy machine) to detect the bit 1010 and also I need to code it in verilog. Here is a picture of my state machine: So, I created the state machine and Now I ...

verilog xilinx state-machines

asked Feb 3 at 5:30

cmelo

13

0

votes

1answer

146 views

pulse width modulation

I need help on number one of this practice assignment. I barely learned about this so it is kind of hard me to understand it right now. So any advice or help is appreciated. I want to determine the ...

pwm verilog xilinx counter delay

asked Jan 31 at 3:39

cmelo

13

2

votes

1answer

52 views

What is the purpose of a “BUF” in Xilinx ISE schematic?

I'm working on a schematic for a Xilinx CPLD using ISE. The schematic has a triangle symbol labeled "BUF" before every output, and also between some other nets. I can't really tell why some ...

xilinx programmable-logic ise

asked Jan 28 at 21:11

samt1903

132

0

votes

0answers

114 views

FPGA ft232h/ft2232h communication problem

I am trying to output an image from a Kintex 7 fpga using the ft232h chip. What's supposed to happen in this process is: the fpga must wait until some input pin txe# goes down, then the fpga should: ...

fpga xilinx ftdi timing-analysis

asked Jan 26 at 14:38

Ran

42

3

votes

1answer

343 views

Vivado is removing registers which will be used

I am working on a verilog program that I want to have display some sort of audio waveform (captured from my microphone) over a VGA. I use the following module to shift in new audio samples, and swap ...

fpga verilog xilinx vivado

asked Jan 24 at 23:59

chasep255

2697

0

votes

1answer

46 views

Displaying signals in testbench from counter VHDL

Say I have a count signal in a counter VHDL file and want to display this in my simulation output, what would I have to do to my testbench to output such data?

vhdl simulation xilinx

asked Jan 24 at 15:07

Gaddi

52

0

votes

1answer

82 views

Generated clock constraints in vivado

I created my own clock since I need a 2Mhz clock and the clock generator IP wont let me go bellow 6Mhz. I created a clock divider module. ...

fpga verilog xilinx vivado

asked Jan 22 at 14:35

chasep255

2697

1

vote

1answer

52 views

Is $realtobits synthsizeiable?

I have been trying to figure out why my verilog program is not working for hours. To test it I just added some constants as inputs to my module and I am using the integrated logic analyser to check ...

fpga verilog xilinx vivado

asked Jan 22 at 1:44

chasep255

2697

0

votes

0answers

70 views

Using on board SPI of Basys 3 to store custom data

I have a Basys 3 board which has an on board SPI flash memory. Configuration bitstream of the implemented logic can be written to this memory through vivado. Reference manual of the board says that ...

fpga vhdl xilinx vivado artix-series-fpga

asked Jan 20 at 10:46

srhat

41

0

votes

2answers

96 views

creating a bcd squarer using verilog

Basically, I am using a lookup table to output in bcd the square of a single digit bcd. The problem that I have is that it is not outputting the correct answer. For example: the result I get for the ...

verilog xilinx hdl binary square

asked Jan 20 at 5:02

CharleBarkely123

11

1

vote

1answer

64 views

Why SATA ALIGN primitive is shifted or swapped on 7-Series GTXE2 transceiver RXDATA output?

I am using a Xilinx 7-Series GTXE2 Transceiver configured as SATA host PHY. This transceiver is interfacing with an SATA Host controller and an SATA Gen1 device. During initialization, I am able to ...

fpga xilinx sata virtex-series-fpga

asked Jan 19 at 5:56

sunni

91

-1

votes

1answer

74 views

Multiplier 4-bit with verilog using just full adders

I am trying to write the test bench part but I don't know how to do it. Basically, I want to test out 0x10 or 5x5. I don't if what I have is right. here's a pic to give you some idea of what i am ...

verilog xilinx hdl adder multiplier

asked Jan 19 at 1:36

CharleBarkely123

11

1

vote

1answer

80 views

How can I constrain an imported netlist in Vivado?

I have a pre-compiled netlist (created by Xilinx ISE 14.7), which is imported into Vivado 2015.4 and used in synthesis to assemble my complete design. Vivado reports unconstrained paths for the ...

fpga xilinx synthesis vivado timing-analysis

asked Jan 16 at 0:27

Paebbels

2,2451323

2

votes

1answer

69 views

Configuring multiple FPGA using JTAG

I have 2 devices, a Spartan 3 and a Spartan 6. I am trying to configure both of them through JTAG. One way to do this is to daisy chain the devices and use boundary scan. However , one thing I still ...

fpga xilinx jtag

asked Jan 12 at 5:28

red car

1086

0

votes

0answers

43 views

Index in block ram is offset by one from position of write

I am having an issue with block ram I am using to create a table to powers of a 64 bit floating point number. I store powers between x^1600 and x^-1600. For some reason when I try to read the table ...

fpga verilog memory xilinx

asked Jan 11 at 4:17

chasep255

2697

2

votes

1answer

79 views

Do I need a license to design IP cores with AXI interfaces?

Many IP cores especially from Xilinx have an AXI interface from ARM. (AXI, AXI-Lite, AXI-Stream, APB, ... are parts of AMBA - ARM's bus architecture). The AXI interface standard is free for download ...

arm xilinx hdl licensing

asked Jan 10 at 21:38

Paebbels

2,2451323

1

vote

2answers

54 views

Xilinx IP for delaying data

I am working on a block design to compute the coordinate in the complex set represented by a pixel. Given an x and y pixel value, the step size, and starting x and starting y I need to compute a ...

fpga xilinx vivado

asked Jan 9 at 4:09

chasep255

2697

0

votes

0answers

50 views

Xilinx ISE ERROR:Xst:2369 - Empty project file “C:\xxxx” what is it about?

I am trying to see the schematic output of my verilog module in Xilinx ISE. However, I am getting this silly error: ERROR:Xst:2369 - Empty project file "C:\Users\aozel\Desktop\Verilog ...

verilog xilinx ide xilinx-sdk

asked Jan 8 at 9:49

Alper91

43515

0

votes

0answers

54 views

I get error in vivado when I try to use source clock of generated one

I want to have two clocks in my project. One that sends output to a VGA and runs at 25 Mhz and another which runs my mandelbrot set calculation at a higher frequency. Here is the code I have. ...

fpga verilog clock xilinx

asked Jan 6 at 13:55

chasep255

2697

0

votes

1answer

66 views

FPGA VGA driver not working

I am not really sure what is wrong with my code bellow for a vga. All I want the program to do is display a solid color on the monitor. I want to use the switches on my card to change the color ...

fpga verilog xilinx video vga

asked Jan 4 at 16:31

chasep255

2697

2

votes

0answers

114 views

Vivado Webpack VS Design Edition

Right now I am using Vivado design edition which I got for free with my diligent basys 3 FPGA. I am currently looking to upgrade my card to Nexys Video which has a lot more features. ...

fpga xilinx vivado

asked Jan 2 at 16:14

chasep255

2697

0

votes

0answers

33 views

Strange verilog errors in vivado

I am trying to make a floating point module to take the integer power of a double base. I want to compute it using x^y = e^(y*ln(x)). I am using the non-blocking floating point IPs provided by ...

fpga verilog xilinx vivado

asked Jan 1 at 20:00

chasep255

2697

1

vote

1answer

59 views

Why do I get a “[Synth 8-5413] Mix of synchronous and asynchronous control for register” warning in Vivado?

The code bellow is to take the reciprocal of a fixed point number using Newton's method. When start is asserted the state machine enters the estimate state. To get ...

fpga verilog xilinx vivado

asked Dec 29 '15 at 23:20

chasep255

2697

3

votes

1answer

50 views

Error when passing wire of different size to module input

I have a module to display a base 10 number on my 7-Segment display. ...

fpga verilog xilinx

asked Dec 25 '15 at 23:07

chasep255

2697

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