How can assign a synthesizable string to a byte array in SystemVerilog?

Question

I want to initialize a byte array (or any other possible type) to a long string. For example define: string str = "abcdefg". I read these two links (1 & 2) but I couldn't find a simple way. These are two hard code ways which I found:

1_ byte str [0:7]; = '{"a", "b", "c", "d", "e", "f", "g", "h"}; This is not an appropriate way, because the string is very long in my real application and I can't write them letter by letter.

2_ Using string type :string str = "abcdefg". But it can only be simulated and isn't synthesizable. Quartus just allows defining string in function or task. So I use the function getStr() for initializing string :

typedef byte string_t[0:7];

function string_t getStr();
    int i;
    string tmp_str = "abcdefgh";            
    string_t str;

    for(i=0; i<8; i=i+1)
        str[i]=tmp_str[i];

    return str;
endfunction

and use it in my code :

byte str [0:7];
always @(posedge clk) begin 
     str = getStr(); // str will be "abcdefg" after getStr() return it.
     //The rest of the code...
end

I think there must be a better and simpler way for initialize a string in SystemVerilog. If you know it help me. Thanks.

Answer 1

You should be able to do this without using string types. Just use a bit-stream cast

string_t str = string_t'("abcdefg");

This works because a string literal (what is enclosed in "") is interpreted as a 64-bit integral value, and as long as the target variable has the same number of total bits, the bits will be streamed from the 64-bit integral to the fixed array of 8-bits X 8-elements array.