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lATCH based clock gating

can anyone tell me the verilog coding and simulation for this design using modelsim software..i had tried a lot by the following coding but i can't get the correct result..please i need it for my reference.

module SD_L(in,clk,rst,q,out);
  input in,clk,rst,q;
  output out;
  reg out;
  wire k1,k2,k3;
  assign k1=in||q;

  SD_dl m1(.enable(k1),.q(k2));

  assign k3=k2&clk;

  always@(posedge clk)
  begin
    out<=q;
  end

  SD_dff m2( .d(in),.clk(k3),.rst(rst),.out(q));

endmodule
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up vote 1 down vote

You create k3 as "clk & k2", but then in your flip flop you have always @ (posedge clk) instead of always @ (posedge k3).

Incidentally, as a design practice you should consider using a flip-flop with an enable signal instead of a gated clock.

Also, your schematic shows one latch and one flip-flop, while your Verilog apparently has three storage elements: one instantiated latch, one instantiated flip-flop, and one inferred flip-flop.

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up vote 0 down vote

as shown your circuit has some issues. In particular, a latch has 2 inputs and you only show 1.

a latch has an enable and a data input.

reg q;
wire d;

always @(latch_en or d) begin // corrected
   if (latch_en) q <= d;
end

also, is that an XOR gate or an OR gate? your diagram shows XOR, but your code shows OR.

share|improve this answer
    
A D latch should be always @(en or d) if (en) q <= d; – The Photon Mar 15 at 17:58
    
you are correct! brain-fart! – hwengmgr Mar 15 at 18:01

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