A Field-Programmable Gate Array (FPGA) is a logic chip that is configured by the customer after manufacturing—hence "field-programmable".
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1answer
22 views
operand isolation in RTL
I'm trying to build some low power circuits at the RTL level. How would I go about coding operand isolation so that the synthesis tool (ASIC/FPGA) recognizes it. Assuming the spec requires the output ...
0
votes
3answers
39 views
Linear Rise exponential fall pulse generator
For a neutrino detector related experiment, I need to design a circuit which generates the pulse similar to the detector. This is required to test the front end electronics.
Here are my final goals:
...
0
votes
0answers
19 views
How to assign pins of Altera Cyclone II to 7 segment?
I am quite new to FPGA and I want to design a 1-digit counter on a 7-segment on an Altera development board. What I have done so far was to schematically design a bcd to 7-segment decoder in Quartus ...
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0answers
16 views
Using TCL (or other Script) file in Quartus to automate circuit creation
I have various simple modules (Verilog) written and included in my Quartus project file.
Lets say each such module receives a 8 bit input, increments the value and outputs the new value.
Depending ...
-1
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0answers
39 views
ADC as an FPGA input? [on hold]
I am currtently trying to buid a PID controller for a servomotor in my SmartFusion2 FPGA, and I would like you to help me with something. It may look like a silly question, but I am a novice in this ...
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0answers
43 views
Xilinx FPGA editor + Relate to Design
I am trying to learn a little more in depth about Xilinx place and route and how everything works. I have made a very simple schematic design and am looking at the result on the board using the FPGA ...
-3
votes
1answer
45 views
What are the applications of DMA in FPGA? [closed]
What are the applications of DMA in FPGA?
on what type of projects is it can be used?
2
votes
3answers
85 views
Are there any standard FPGA internal buses?
Are there any standard FPGA internal buses?
I've always used some sort of bidirectional bus between my internal blocks, but is there a standard way of doing this?
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votes
0answers
32 views
Interfacing a TM4C123 with a Basys3?
I'm trying to build a shell-based real-time OS on a TM4C123 LAUNCHPAD. I already have the kernel and file system done, and I was hoping to add interactivity to this implementation.
I was hoping to ...
0
votes
1answer
27 views
HDMI (TMDS) output with Digilent Atlys - examples do not compile with ISE 14.7
I'm working on XAPP495 on Digilent Atlys board with ISE 14.7
I want to run and test "vct_demo" coming with the XAP 495. I tried to compile it (with ISE 14.7) and failed because of the following ...
0
votes
1answer
16 views
Is there support XC5VLX110 list in ISE Project setting?
I'm just trying to setup ISE envirmonent.
But There's not XC5VLX110 in Device list at the Project Settings in ISE as below picture.
What should I do for solving in this situation?
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0answers
24 views
XAPP495 problem [duplicate]
I'm working on Digilent Atlys board and I want to implement XAPP495 , but I just want to use one input which I will take it from HDMI out on my laptop and one output which I will connect it to monitor
...
-1
votes
1answer
40 views
Designing a basic computer with Quartus II and FPGA [closed]
I designed an 8-bit system in Quartus II that can run on the Altera DE2 in my this online coursework. I make an 1 bit ALU, then a 4 bit ALU and then an 8-bit ALU. I designed a multiplexer, an adder, a ...
-1
votes
1answer
64 views
How to establish a communication between FPGA and CPU, in real-time? [closed]
I am working on a project that involves FPGA and CPU communication(in real-time - i.e, CPU and FPGA should function together).
I have already designed and tested the UART communication protocol on ...
0
votes
0answers
65 views
Lattice MachXO3L: MIPI CSI2 bridge
I would like to design a MIPI CSI2 bridge with a MachXO3L.
I leverage the LVDS25 input/output of this FPGA family with the adequate resistors for HS traffic. (I think) I don't care about LP as the ...
-4
votes
1answer
60 views
Problem with implementation XAPP495 [closed]
I'm working on XAPP495 to show a signal which is throughput of a HDMI signal from my Laptop
I do this steps:
created a new ISE project
added all of the .v files from XAPP495
added dvi_demo.ucf
set ...
0
votes
1answer
44 views
Why the output signal from the counter seems to be not driven?
I've written a memory module for an application. In order to address each memory location a simple 6-bit counter is used. I have tested most of the components (including the counter) and they seem to ...
0
votes
2answers
74 views
Designing a open drain LED driver
Will this open drain LED driver circuit work ?
The open drain IO is governed by the following equation
0.5 <= V_LED_OUT <= 3.6 V (abs_max)
V_LED_OUT is the voltage from open drain IO pin to ...
-1
votes
1answer
16 views
Detecting a signal to meet criteria
Not sure if this belongs here.
Using FPGA:
Lets say I get a trigger input to my system.
I want to declare that an edge is part of my signal if I get it every X \$ \mu \$s time. (lets say 1\$ \mu ...
6
votes
2answers
167 views
Is anything besides rx and tx actually used in rs232 nowadays?
Whenever I come across a PIC or even a FPGA project that is communicating over the serial port with a PC; only Rx, Tx and power are connected on the 9 pin connector and the other pins/signals are ...
0
votes
0answers
18 views
Flashing NIOS II with SPI at boot
I have a Altera FPGA, which is configured (programmed/flashed) at startup by SPI from a processor runing embedded linux.
If I put a NIOS processor in the fpga, is it possible to flash the NIOS ...
0
votes
2answers
67 views
What the FPGA dev board to choose: Xilinx or Altera? [closed]
I'm very new to programmable logic world and have never worked with any HDL languages, but I certainly want to get started with FPGA. At the moment the goal is to develop/simulate simple 8bit CPU and ...
0
votes
1answer
69 views
VHDL - 10% Duty Cycle
I need to generate 500Hz from 50MHz clock frequency. I already got it. My problem here is how should the code to be adjusted if I want to change the duty cycle to 10%?
Thank you.
...
4
votes
1answer
80 views
Should I use an FPGA output for an MCU Clock?
We are laying out a board that was designed ages ago, the main purpose of the update is for part obsolescence. The board has several PIC uC's on it as well as an FPGA. Each of the PIC's needs a ...
1
vote
1answer
25 views
Implementation of NIOS Softcore alongwith HDL modules on Aletra Cyclone IVGX
My question is not on 'how can' but 'if can'. So I believe people with sufficient experience on any FPGA family might be able to help me out here.
Problem Statement: I need to model a very basic ...
3
votes
1answer
58 views
Max number of logic units / gates per logic-unit-output wire: FPGA
I couldn't find any info about this. Is there a general rule or does it change for all vendors(altera or xilinx)?
Lets assume I have a flip flop and I want to wire 10 flip-flops to its output. ...
0
votes
1answer
21 views
Vivado: Block Design sub module
I'm working on a Video processing project with Vivado 2015.2 on a Zynq device.
My block design starts to get huge and hard to read. As I have several times the same pipline implemented, I would like ...
-3
votes
0answers
29 views
How to implement a 3D converter software into an external main PCB board as a module?
I am working on a project which requires 2D - 3D conversion directly to screen. So in the system, input is 2D video coming in DisplayPort format and we need to convert it to 3-D(for a given depth ...
0
votes
1answer
58 views
An overall PWM system by using FPGA [closed]
I need to combine this 3 coding to form one whole PWM system by using FPGA. I tried it, there is no error, but the process is not synthesizable. Please help me.
Thank you.
This is code for ...
-2
votes
0answers
41 views
Matlab filter to vhdl
I want to filter a sine wave signal using Altera FPGA(cyclone IV). The sine wave is first converted by an ADC with Fs= 20Mhz, then stored into a register inside the FPGA. The frequency of my signal is ...
0
votes
0answers
55 views
Memory Interface with a Multiplexed Address/Data Bus
I want to implement a memory interface in VHDL between an FPGA and a processor. The address/data bus is a 16-bit multiplexed bus with an ALE, write protect and BusWait. According to the NVIDIA Tegra 3 ...
4
votes
3answers
54 views
Where do the mux select lines come from in a CLB?
I am trying to understand the inner workings of a CLB in an FPGA but I can't seem to find out exactly how the routing multiplexers WITHIN the CLB work. Well, I understand how they work and what they ...
0
votes
0answers
34 views
lwIP initialization hangs when configuring TEMAC
I am working on a my master thesis, designing an FPGA solution, and have run into a very resilient problem. I will try to provide as much information as possible, in the hopes that someone might have ...
0
votes
0answers
22 views
VHDL - how to get signals from inside a uut in a testbench? [duplicate]
I am writing a testbench for a component I created. In order to debug it, I would like to write the value of some of the internal signals to a textfile.
I know it is perfectly possible to write the ...
1
vote
3answers
236 views
Why would you want to write to a file when writing VHDL? [closed]
I have never so far been in the need to write to a file when making a testbench in vhdl. Seeing the signals being plotted has always been enough so far.
Could someone please give me a case or the ...
0
votes
0answers
33 views
CFI flash interface in verilog
I am working on an Intel’s CFI - Flash (28F640J3) interface in verilog.
I have written a code and tested it for many commands; read, write, erase.
But I am facing problem with 'Write Buffer’ and read ...
0
votes
2answers
67 views
Simple LED FPGA Circuit
I am new to digital design, and have recently purchased a Bemicro MAX10 FPGA development board to help get my feet wet. I am trying to learn VHDL, and have downloaded a few PDFs to get me started. The ...
0
votes
0answers
42 views
use of ISD4002 SPI with FPGA
I am trying to build a circuit that would be some kind of INTERCOM and will be controlled by FPGA (cyclon 2 by altera ) .
Because I need to have multi voice channels I choose ISD4002 because in my ...
0
votes
0answers
18 views
How to view Nios 2 assembly code?
I use the Altera DE2 FPGA that can run my C program. If I want to view the generated assembly, how can I do it? It's usually some flag for gcc and I use Nios 2 IDE ...
3
votes
1answer
68 views
AM335x FPGA Memory Integration
I'm currently designing a digital mixing console. We have a somewhat large number of ADCs and DACs (more than the multi channel audio serial port on the processor can handle). We decided the solution ...
1
vote
2answers
54 views
How to get a default UCF file of Xilinx Virtex-5 XC5VLX110?
How to get a default UCF file of the Xilinx Virtex-5 XC5VLX110?
It doesn't seem to be anyhere. If I have to make it by myself, would you let me know how to ...
0
votes
0answers
56 views
How to divide 50MHz down to 5Hz in VHDL on Xilinx FPGA [duplicate]
How to divide 50MHz down to 5Hz in VHDL on Xilinx FPGA
I have a Xilinx FPGA board, with a 50MHz crystal. I need to divide that down to 5Hz in VHDL. How do I do this?
0
votes
0answers
16 views
Hardware Co-Simulation using ml605 with ISIM simulator …?
I am trying to do RTL(verilog HDL) and Firmware(System C) Co-Simulation with ISIM Simulator using VIRTEX-6 ML605 FPGA board. I am unable to run co-simulation.
I have reffered the document " Hardware ...
0
votes
0answers
34 views
Possible to Use a Papilio One 250k Logic Analyzer as an FPGA?
I've just bought a Papilio One 250k logic analyzer, which seems to be based on an FPGA dev board of (nearly) the same name. Can/should I try to use this as an FPGA board? Could I easily flash my own ...
1
vote
2answers
70 views
Correctly initialize a shift register (Verilog)
I've been struggling with a very simple Verilog program. It's a 4 bit shift register that gets rotated at every clock cycle and drives four LEDs. (As you can tell I'm new to FPAGs and HDLs.)
The ...
1
vote
2answers
114 views
Working on an FPGA without an IDE [closed]
I've been programming microcontrollers for about 5 years now. In my current MCU development workflow, I use emacs to edit my firmware, I compile with arm-none-eabi-gcc, and I flash code with a segger ...
6
votes
2answers
204 views
Do I need to reset my FPGA design after startup?
I usually initialize state registers of my FSMs by specifying an initial value in my VHDL code, so that, I do not require a reset pulse after startup of the configured FPGA. The following example ...
1
vote
1answer
108 views
Generating video with ZYNQ, using IP block design?
I am trying to implement a video streamer on Digilent ZYBO board that has Xilinx ZYNQ 7010. By the way, reason of this thing is to test the quality of an encoder board. What I want is to:
Generate a ...
0
votes
0answers
52 views
Procedures or structural architecture - which is preferable for synthesis in VHDL?
I'm writing VHDL code which I would like to implement on an FPGA. Currently I have written separate architectures for adders, multipliers etc and combined them all using a structural architecture in ...
1
vote
1answer
43 views
Synthesisable alternative to the wait statement in VHDL
I'm writing VHDL code for a filter which I want to implement on a Spartan 6 FPGA. When I tried running a testbench for my code, one of the processes entered an infinite loop, so I added a wait ...
