Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.
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How to find minimum among variables with excluding variables having zero values in Verilog?
I have 6 variables names D1,D2,D3,D4,D5,D6. I wanted to find minimum among them but excluding the zeros if any present.
I did same in MATLAB by using below command:
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3
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1answer
49 views
Dividing a clock in Verilog - is it OK?
Dividing a clock down in Verilog is a basic exercise, and there are loads of answers online about how to do it. What I want to know is whether it is OK to use a clock that has been divided down using ...
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2answers
64 views
Synchronuous Combination Lock
I'm trying to implement a synchronous combination lock that will unlock once it receives "101011" using verilog. It has one input: x, and three outputs: unlock, ready, and error. Following these ...
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1answer
51 views
Non-Wraping Up-Down Counter
I'm trying to implement a synchronous up-down counter in verilog with the following rules:
Counter only changes on rising edge of clock
When reset=1, count goes to 00, normal operation when reset=0 ...
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1answer
20 views
Change array to individual outputs
I'm trying to design a synchronous sequential circuit to implement a tail light controller for a 1965 Ford Thunderbird using verilog as shown below (included with the state diagram).
I have the ...
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41 views
Using 4-Channel ADC With FPGA
I am using an ADC084S101 4 Channel 8-bit A/D Converter to sample 4 different analog voltages. The ADC is being driven by a Nexys3 FPGA. I am having issues getting the ADC to cycle through all four ...
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2answers
54 views
Assigning x in verilog
Assume there exists a 1 bit data output port and a 1 bit dataValid output port for a module. Is it OK to assign 1'dx to the data output when dataValid is assigned 0? Will this create synthesis issues?
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1answer
20 views
User defined data type in Verilog
I have always used VHDL and now need to use Verilog, so I'm learning Verilog. . .
How can I define and use user-defined data type in Verilog for state machines.
for eg : In VHDL I would write ...
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1answer
69 views
Displaying Characters In Verilog With VGA
I'm taking a intro to ECE course as a CS student and for a final project we are to design a game coded in Verilog using the VGA display on a DE1-SoC board.
I decided to create a hangman game but I ...
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1answer
34 views
Generating Channel Select for Multichannel ADC
I am using a FPGA to control a 4-channel ADC (ADC084S101) to sample four different analog voltages. In order to tell the ADC which channel to sample next, there is a control register that can be ...
1
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1answer
46 views
Asynchronous Down Counter using D Flip Flops
After fixing my Up Counter, I'm having troubles writing structural verilog code for an Asynchronous 4-bit Down Counter using D Flip Flops.
Here's the D Flip Flop code (which was tested and works):
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36 views
Asynchronous 4-bit Up Counter using D Flip Flops
I'm trying to write structural verilog code for an Asynchronous 4-bit Up Counter using D Flip Flops.
Here is my D Flip Flop Code made from this image:
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2answers
46 views
Is there some flag / pragma which can help me in detecting bogus variable names in a module definition?
[icarus verilog]
Is there some flag / pragma which can help me in detecting bogus variable names in a module definition?
Consider the following code fragment ...
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2answers
53 views
Increment operation in 24 bit counter
This is a 24 bit counter verilog program. What is the function of highlighted operation? Do we add 1 to the least significant bit? How can we know that the addition was done to the least significant ...
3
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1answer
45 views
HCI UART ? what's the difference with simple UART?
For now, I'm sending bytes from FPGA (verilog) to serial at 115200 bps.
I would like to send at higher speed and connect to a bluetooth module (RN42).
UART (SPP or HCI) and USB (HCI only) data ...
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0answers
19 views
Event Debug Mode error when performing mixed Verilog/VHDL simulation in VCS
I am getting the following error:
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1
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1answer
76 views
AND Gate and posedge CLK ? simple question
I'm trying to do the seq system as the picture, I'm sure it's simple but I don't remember the "gate" of this.
This clock cond will be used for sending bit in ...
2
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0answers
72 views
Two different ways of writing the same thing but generating different behaviours in Verilog
I have a part of Verilog code that is basically trying to synthesize a flip-flop. I have been experimenting and it seems that I can come up with two ways of writing it.
The first way being :
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1answer
20 views
Verilog outputting specific bit from register to output; getting constant 1's
I am trying to create an program that bit bangs a value from an FPGA to an arduino. In the module I created, every other clock cycle, the FPGAdata output should be set to the next bit of t. The ...
0
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1answer
31 views
Task doesn't work in verilog
I created a module that first sorts a byte array then choose last element as minimum.(just for practice). When I moved sort to the task block, it doesn't worked as well as before. How can use task ...
2
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5answers
135 views
Blocking vs Non Blocking Assignments
I have been having a really hard time understanding the difference between blocking and non-blocking assignments in Verilog. I mean, I understand the conceptual difference between the two, but I am ...
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1answer
55 views
D flip flop in verilog
When i tried to code the below flip flop, the program failed. I'm using altera .
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1answer
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53 views
What is the difference between an array and a bus in Verilog?
I have been learning Verilog and Vivado at school, and I am now very confused by the usage of busses and arrays. Can anyone clarify the following?
What is the difference between an array and a bus?
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38 views
4-bit Comparator Verilog Code
I need to create structural verliog code to make a four bit comparator (out of four behavioral-coded one bit comparators). But I've only gotten my greater than output to work.
I'm using this circuit ...
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2answers
68 views
Synthesizeable D Flip flop for FPGA
Having played around with Verilog for some time now, I decided to graduate to implementing designs on Alltera CycloneIV FPGA using the Quartus suite.
Starting with a simple D flip flop, I face the ...
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45 views
CFI flash verilog write read
I'm trying to write a controller for an Async CFI flash in Verilog. I could read the ID but couldn't write and read 1-word data. Also tried to erase the flash before writing but didn't work.
The ...
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4answers
120 views
How to make a Karnaugh Map with “don't care” inputs?
I know that don't cares mean that it doesn't matter whether it is a 0 or a 1 and when don't cares are just outputs I can kind of understand how they work. But I am having a really hard time ...
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37 views
How to instantiate Mig file to read and write data?
I want to write and read data for ddr2 for vertex 5 .I got instantiating file and instantiated in my main logic with inputs sys_clk_p,sys_clk_n,clk200_p,clk200_n,sys_rst_n. but still not understanding ...
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1answer
30 views
Compact multi-cycle adder for fpga: adding 1 to wide counter
I want to implement some kind of event counter in my FPGA design (Vendor-A or Vendor-X). I have several dozens of signals: half are 1-bit and other half of them is 5-bit. Signals are located in ...
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1answer
76 views
how to find square root of a number by using babylonian method [closed]
how to find the square root of number by using babylonian method equation: Xn+1=1/2(Xn+(s/Xn)) by using verilog code any one help me ........I have written a code but its not synthesis not running.
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1answer
35 views
What exactly does a High Impedance imply in Verilog?
When would we want to use High Impedance signals?
In simulation, what causes the result of a high impedance signal? Seeing as its generally a bad thing, what should be looked for in terms of ...
6
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1answer
139 views
I want to implement a math equation in FPGA, should I describe a CPU or can I do it just by code?
For a school project I'm trying to implement an equation for example like this:
(EDIT)
B = ((A + 2) * |A - 10|) / (c * c)
everything is unsigned binary values, ...
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0answers
35 views
Verilog row by column multiplication
I'm trying to design a generic row by column 32bit multiplier (in other words a vector) using inbuilt multipliers and adders. I have writen the code in verilog but I'm not sure if my method works as ...
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1answer
55 views
Modeling a Time to Digital Converter in Verilog-AMS
I'm trying to write a TDC model in Verilog AMS. I'm really new at the AMS part of Verilog.
The problem I'm running into is in assigning the final state of the TDC to the outputs. Below I present the ...
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1answer
35 views
Port Connection Rules in Verilog
I am a beginner in Verilog
I would like to know why the port connection rules as outlined in the attached description are necessary.
Why must inputs be internally of a net type signal? And ...
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2answers
97 views
8 bit counter from T Flip Flops
I'm trying to build an 8bit counter in Verilog. I specifically need to create a module that I instantiate 8 times. I have followed the diagram below (and assumed that I can just build on it to make it ...
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1answer
51 views
Quartus: Error (12004): Port z does not exist in primitive x of instance y
I cannot find any source for this error, any help much appreciated!
Error: Error (12004): Port "a" does not exist in primitive "tff" of instance "t1"
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1answer
77 views
Where to start on emulating a Pulse Width Modulation
This is a homework assignment and I don't really want the whole answer just a place to start on this assignment. Here's what I'm supposed to do.
"Emulate a PWM (pulse width modulation) generator. ...
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1answer
54 views
Verilog SPI module functioning in unpredicted ways
I am currently trying to implement a simple SPI Master module in Verilog using Quartus Prime Lite V15.1.0 Build 185 for compilation and Simulation Waveform Editor as my simulation tool. The module has ...
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2answers
57 views
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2answers
37 views
In Verilog Synthesis, Creating several Instantiation of a Module is the same than instantiate several modules with same content?
I wonder if there is a difference between creating several instantiation of a single module and to instantiate different modules (with identical hardware code) only one time.
For example, I want to ...
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2answers
52 views
Output in unknown state even though specified in verilog
I am having some troubles with creating an edge detector in verilog. So far I've come up with this:
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1answer
60 views
How to use UART port for sending status in verilog
I am developing various verilog modules with state machine for a fpga board.
When i have done simulation of the modules i have used "$display" to get what is happening in the module or otherwise the ...
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2answers
116 views
32 Bit Increment Circuit and Verilog Program
I have to build a circuit that stores a 32-bit number. The circuit features a control signal inc that, when active, increments the stored value by 3 in each cycle. If inc is 0, the circuit simply ...
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0answers
64 views
T Flip Flop Verilog
I don't quite understand flip flops that well so I just wanted to see if this verilog code I wrote makes sense and if the outputs are what are expected from a T Flip Flop
verilog code:
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3answers
37 views
Verilog assign result of module
I am trying to take the result of a module and assign it to an input of another module, however I keep getting an error about declaring net types. I feel like I'm missing part of the syntax rules ...
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1answer
60 views
Verilog 8 Bit ALU
Here's what I have so far but I'm stuck with what to do for the f values for the last two and whether the if statement syntax is correct. Any tips?
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1answer
73 views
Modelling Circuit from FSM using Verilog
I am trying to understand the concept of modeling a circuit from a FSM in Verilog.
I have tried to write down the procedure that I have used in the image below just to make sure that I did it right:
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