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I need to combine this 3 coding to form one whole PWM system by using FPGA. I tried it, there is no error, but the process is not synthesizable. Please help me. Thank you.

  • This is code for FreqDivider200Hz

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FreqDivider200Hz is
port(
clock   : in STD_LOGIC; -- 50 Mhz
clear   : in STD_LOGIC;
  freq1 : out STD_LOGIC
);
end FreqDivider200Hz;

architecture Behavioral of FreqDivider200Hz is
signal adjfreq: STD_LOGIC_VECTOR(16 downto 0) := "00000000000000000";
signal adjclock : std_logic := '0';

begin

         freq1 <= adjclock;

countClock: process(clock,clear)
begin
if (clear = '1') then
    adjfreq <= "00000000000000000";
elsif(clock'event and clock = '1') then
    -- Flip a the output once every 125,000 cycles (400Hz)
    -- to give a 200Hz output with 50% duty cycle
    if (adjfreq = "11110100001001000") then  
        adjfreq <= "00000000000000000";
            if adjclock <= '0' then
            adjclock <= '1';
            else adjclock <= '0';
            end if;
        else 
        adjfreq <= adjfreq+1;   
    end if;
   end if;
  end process;
 end Behavioral;

  • This is for code for FreqDivider400Hz

    enter library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FreqDivider400Hz is
port(
clock   : in STD_LOGIC; -- 50 Mhz
clear   : in STD_LOGIC;
  freq2 : out STD_LOGIC
);
end FreqDivider400Hz;

architecture Behavioral of FreqDivider400Hz is
signal adjfreq: STD_LOGIC_VECTOR(15 downto 0) := "0000000000000000";
signal adjclock : std_logic := '0';

begin

freq2 <= adjclock;

countClock: process(clock,clear)
begin
if (clear = '1') then
    adjfreq <= "0000000000000000";
elsif(clock'event and clock = '1') then
    -- Flip a the output once every 62500 cycles
    -- to give a 400Hz output with 50% duty cycle
    if (adjfreq = "1111010000100100") then  
        adjfreq <= "0000000000000000";
            if adjclock <= '0' then
            adjclock <= '1';
            else adjclock <= '0';
            end if;
        else 
        adjfreq <= adjfreq+1;   
   end if;
  end if;
 end process;
end Behavioral;code here

  • This is code for 2x1 multiplexer

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux2to1 is
Port ( freq1 : in  STD_LOGIC;
       freq2 : in  STD_LOGIC;
       sel : in  STD_LOGIC;
       y : out  STD_LOGIC);
end mux2to1;

architecture mux2to1 of mux2to1 is

begin

p1: process (freq1, freq2, sel)
begin
if sel = '0' then
        y <= freq1;
else
        y <= freq2;
end if;
end process p1;
End mux2to1;

  • This is code for overall system

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity OverallSystem is 
Port ( clock : in STD_LOGIC; 
         clear : in STD_LOGIC; 
         sel : in STD_LOGIC; 
         y : out STD_LOGIC ); 
end OverallSystem;

architecture Behavioral of OverallSystem is
component FreqDivider200Hz is
port(
     clock   : in STD_LOGIC;
     clear   : in STD_LOGIC;
     freq1 : out STD_LOGIC);
end component;

component FreqDivider400Hz is
port(
     clock   : in STD_LOGIC;
     clear   : in STD_LOGIC;
     freq2 : out STD_LOGIC);
end component;

component mux2to1 is
Port ( freq1 : in  STD_LOGIC;
       freq2 : in  STD_LOGIC;
       sel : in  STD_LOGIC;
       y : out  STD_LOGIC);
end component;

signal freq1 : std_logic; 
signal freq2 : std_logic;

begin

chip1 : mux2to1 port map ( freq1 => freq1, freq2 => freq2, sel => sel, y => y );
chip2 : FreqDivider200Hz port map ( clock => clock, clear => clear, freq1 => freq1 );
chip3 : FreqDivider400Hz port map ( clock => clock, clear => clear, freq2 => freq2 ); 

end Behavioral;
share|improve this question

closed as unclear what you're asking by PeterJ, Peter Smith, uint128_t, Asmyldof, Daniel Grillo May 2 at 11:18

Please clarify your specific problem or add additional details to highlight exactly what you need. As it's currently written, it’s hard to tell exactly what you're asking. See the How to Ask page for help clarifying this question.If this question can be reworded to fit the rules in the help center, please edit the question.
    
PWM is just a timer and comparator. I would help better, but i am really not in a mood of code reading. You could ask a more clear question. – Gregory Kornblum Apr 30 at 5:25
    
This is a Q&A site. So to write an answer we need a precise question from you. – Paebbels May 1 at 11:30
up vote 1 down vote accepted

See code below to combine 3 files together.

--- top.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top is
port ( 
    clock : in  STD_LOGIC;
    clear : in  STD_LOGIC;
    sel   : in  STD_LOGIC;
    y     : out STD_LOGIC
);
end top;

architecture beh of top is

signal freq1 : std_logic;
signal freq2 : std_logic;

begin

chip1 : entity work.mux2to1
port map(
    freq1 => freq1,
    freq2 => freq2,
    sel   => sel  ,
    y     => y
);

chip2 : entity work.FreqDivider200Hz
port map( 
    clock => clock,
    clear => clear,
    freq1 => freq1
);

chip3 : entity work.FreqDivider400Hz
port map( 
    clock => clock,
    clear => clear,
    freq1 => freq2
);

end beh;
share|improve this answer
1  
Thank you for your help. I already tried it, but it still have an error. This is the code. – Min_ah Apr 30 at 8:40
    
I cannot see the error .... please attach the error line – tals Apr 30 at 8:47
    
How I can post my code here? – Min_ah Apr 30 at 9:01
    
Just error line (copy/paste) – tals Apr 30 at 9:07
    
I added a little bit the code, there is no error. But for the process synthesis it shows this symbol ! – Min_ah Apr 30 at 9:17

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