The ddr tag has no usage guidance.
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20 views
Choose “safe” section of DDR memory in ZC702 board
I can not fully understand what section of the available external memory is safe to assign for a VDMA on the ZC702 board. I need to dedicate 4MB of memory for the three frames (640*480* 4bytes * 3 ...
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0answers
13 views
DDR2 delay matching
I'm trying to connect a ddr2 to an fpga (Datasheet in x16). I know I need to respect some timing constraints. As I understands things the ddr2 signals are separated into differents groups.
First of ...
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1answer
47 views
LPDDR2 reference design?
I've been trying to interface LPDDR2 ram with my SOC but got confused as to how to connect the CA lines. Does anyone have any reference designs of LPDDR2 for me to go off of?
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1answer
25 views
lpddr2 interface differences between different memory controllers?
The way LPDDR2 connections are done with CA bus is different between these two processors. I thought since LPDDR2 is a JEDEC standard, these schematics should be interfacing with the same lines from ...
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2answers
41 views
Combining decoupling capacitors for sensitive power requirements in LPDDR
I've been looking through a bunch of designs I found online on LPDDR2 interfacing.
What's always confused me is the parallel decoupling capacitors. Why have so many vs just combining that to what you ...
4
votes
2answers
250 views
Weird 240 ohm resistor on zq line to DDR
I've been looking at schematics that interface ddr ram and noticed a weird notation for their zq pull down resistor. What is with the dot at the top as well as the 1%? Haven't seen this before.
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0answers
54 views
What is the difference between LPDDR2-S2 vs S4?
Looking at page 18 of the JEDEC spec on LPDDR2
LPDDR2-S2 also uses a double data rate architecture on the DQ pins to achieve high speed operation. The double data rate architecture is essentially ...
2
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1answer
83 views
What is the more frequent error in DDR Memory?
this is about DDR memory data corruption and not about STUCK address or data lines. If we have a good DDR with no memory stuck issues and we perform lots of writes and reads which type of error is ...
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1answer
69 views
Does a DDR RAM device exist which would allow RAM to be removed and preserved? [closed]
Hello I would like to know if there any device which could preserve content of RAM once removed from a host system and this special device could be connected perhaps by way of USB to another machine ...
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1answer
95 views
Moving a large dataset from the PS to PL on a zynq device?
I am at the moment trying to interface with DRAM on my Xilinx Zynq device such that I am capable of moving a large amount of data from the processing system (PS) side to the programmable logic (PL). ...
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0answers
40 views
Enabling DDR in SD/MMC causes problems? CMD 11 gives a response, but the voltage switch won't complete
I am trying to enable DDR on an SD card (specification above 2.0). The procedure in the specifications is as follows
Execute CMD0 to make the card idle.
Execute CMD8 to enable ask about the voltage ...
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1answer
72 views
What is traffic generator (while using Xilinx Memory Interface Generator)
I am trying to use the Memory controller Block in my Xilinx Spartan 6 FPGA to set up an interface with LPDDR memory. I read the MCB User guide, and I am quite clear about how it works, and how I would ...
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0answers
84 views
Timing constraints for DDR output multiplexer
Consider the following circuit, which multiplexes the d0 and d1 inputs to the y output in ...
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0answers
58 views
GDDR Power Calculation
I'm wondering if there is any publicly available documents or research papers that cover GDDR power estimation?
Micron provides very nice documentation and calculators for DDR up to DDR4, however I ...
3
votes
1answer
190 views
DDR4 frequency decrease if populated with more than one module per channel
I'm curious how one particular company Gigabyte ensures its server motherboards
to run at the maximum supported memory frequency even when there're two or three DIMMs per channel (of coure we're ...
4
votes
1answer
61 views
how does this differential ddr receiver work?
I'm looking at this simple schematic trying to understand how a DDR SSTL receiver works (the one on the left). I get that the input voltage will be compared to Vref and the output will be a ...
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0answers
232 views
Why DDR3 RAS timing have to be greater than RCD + CAS timing?
By definition, tRAS is the minimum delay from when a particular row in a bank is activated, to when it can be closed with a PRE command.
I have seen claims numerous times that tRAS should be > tRCD + ...
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1answer
132 views
DDR interface - SSTL termination
I have a question regarding the DDR SSTL termination.
The JEDEC Standard (JESD8-9B) about the SSTL Interface for DDRs shows two possible termination methods, class I with single parallel termination ...
3
votes
1answer
143 views
What references cover DDR3 layout considerations?
I'm looking for succinct yet correct guidelines for evaluating a DDR3 memory PCB layout. I know that trace length matching, via style and back-drilling, and signal grouping all matter. I know that ...
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2answers
316 views
waveforms showing effect of trace-length matching for SHORT ddr/ddr2/ddr3 traces?
I've seen lots of waveform plots that illustrate the beneficial effect of things like on-die termination, and the effect is unmistakable. For example, see page 6 of this Micron technical note. I'm ...
2
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1answer
211 views
Zedboard 512x512 matrices, % utilization problem
My objective is to read seven 512X512 float matrices from the SD card to the DDR memory (step accomplished already with each matrix occupying around 1Mb), then pass them from DDR to my custom IP block ...
1
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1answer
814 views
MM2S simple transfer gone wrong
I followed some examples and I already managed to make a big S2MM (stream to memory-mapped) transfer via an AXI DMA.
However, now I'm trying the reverse, i.e. to make a simple MM2S transfer to a very ...
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1answer
105 views
Understanding Address Map
Please refer to this image of page 113 of this manual
I'm not understanding this table. From what I can tell, I have from 0010_0000 to 3FFF_FFF of DDR memory, which is 1 072 693 247 bytes and ...
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1answer
58 views
Memory address 32-bit
I'm working with a Zedboard and I'm printing to the screen memory addresses of consecutive 32-bit float numbers.
So the print generates this:
...
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1answer
558 views
how to calculate capacity of the ddr address line
i see the micron data sheet 8-GB,4-GB and 1-GB the address lines are 16,15,13
my question is how to calculate the capacity of the (double data rate type three synchronous dynamic random-access memory ...
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1answer
291 views
How does Xilinx MIG AXI interface map to DDR PHY pinout?
At the bottom of page 156 of UG586 I can understand how the User Address maps to the PHY pinout. However, I can't understand page 155 of the same manual. How does the 32-bit Microblaze address space ...
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2answers
2k views
In an SDRAM how do address rows/columns and rank width and bank width relate to the total memory size?
I have a Micron SDRAM (MT16KTF1G64HZ-8GB). The size of the memory is 8GB. I did some calucaltions and 8GB of data means 2^36 bits capacity. Now when I look in the Micron data sheet, the row address is ...
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2answers
281 views
Series Termination DDR
I was Going through some application notes for the placement of Series termination of DDR and found it should be placed near to the processor.
But if I am not wrong termination resistor are placed to ...
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0answers
157 views
Creating Serial Pressence Detect data from discrete DDR RAM datasheet
I have a board that has soldered discrete DDR RAM chips. The datasheet for the DDR RAM chips is available to me. The DDR memory controller is programmed manually using pre-calculated values.
I have ...
3
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0answers
910 views
Why All DDR's (DDR, DDR2, DDR3) internal clock sets to 200MHz
If we see the DDR Upgrade technology explain below the internal clock of all DDR is set to 200 MHz.
DDR
For example,DDR-400
Efficient frequency data bus is 400 MHz
True clock rate (IO buffer ...
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vote
1answer
119 views
Independence of the two channel architecture of LPDDR4
I'm working on a project involving LPDDR4. I've read the pertinent sections of the recently released JEDEC LPDDR4 spec. I have several questions regarding the independence of the two channel ...
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vote
1answer
375 views
Do I need to reset a DDR's DLL when I change clock frequencies?
I have a system that boots at one frequency and then the main PLL is reloaded to continue boot at a higher frequency. When this is done, the DDR is put in to self refresh. After the main PLL locks, ...
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1answer
843 views
What is DDR software leveling?
What is DDR software leveling ?
How it is different from DDR2 and DDR3 ?
Why it is required and important ?
Is there a hardware leveling ?
I have found some explanation here about DDR3 and a ...
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2answers
350 views
Debugging DDR bus issues
We have an SBC board, in the style of the Leopardboard or Beagleboard, that is misbehaving. It's based on the Leopardboard design (TI-DM368 CPU, DDR2 RAM, NAND Flash).
Developing software on the ...
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1answer
482 views
DDR2 CAS Latency - is it fixed to clock-cycles or time?
We have a (new, prototype) board that is, at best, temperamental. It's using a Micron MT47H64M16HR-25:H DDR RAM, the design reference board uses a Micron MT47H64M16HR-25E:H. Only one letter different, ...
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1answer
891 views
Is there a PCB-layout related reasoning behind DDR memory package and footprint?
BGA DDR packages have a unique footprint. There are two columns of pads on both sides of the device, and an empty column in between.
Is there a reasoning behind the placement of these pads (in ...
6
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3answers
4k views
Interfacing with RAM from a PC, e.g. SDRAM / DDR, to a microcontroller
I'm looking into interfacing standard PC form-factor SDRAM or DDR sticks to a microcontroller, but I can't find any definitive details on how they work in terms of how the bus works. I guess it's ...
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1answer
612 views
Memory IC width vs depth
Given a need for a single 2G × 32 bit DDR3 memory block, which configuration would be ideal and why?
A: Two 2G × 16 bit memory ICs
or
B: Two 1G × 32 bit memory ICs
I think that A ...
5
votes
1answer
5k views
Speed difference between SRAM (Static RAM) and DDR3 RAM
This is more of a computing question, but only electronics geeks would know such things. Today's computers use multiple layers of memory in order to work with data quickly. Currently CPU speeds are ...
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3answers
5k views
Question about trace length matching patterns for high speed signals
A colleague and I had a discussion and a disagreement about the different ways high speed signals can be length-matched. We were going with an example of a DDR3 layout.
All the signals in the ...
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1answer
160 views
Can I use LPDDR with Cyclone III FPGA?
I have seen the Cyclone III datasheet and it claims DDR and DDR2 compatible PHY.
But was looking some good LPDDR chips for my design.
Could I use the PHY inside of Cyclone III with LPDDR ic?
Do you ...
2
votes
1answer
111 views
power down some but not all DDR on a bus? And I'm thinking of DDR3/3L and DDR2.
I'm starting to learn about power managment, and am wondering, can you power off a DDR module on a memory bus while others are still in use? Or does that mangle signal integrity on the bus? I assume ...
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3answers
3k views
DDR1 Layout Considerations - DOs and DONTs
I am novice to high speed design.
Before getting in to DDR, I recently learned about impedance matching and how it is done, likewise I learned about length matching and how it is done.(Baby steps ...
