Generate instance with different string parameters in verilog

Question

When I was config pll_reconfig module in Quartus II, the generate for statement in design have to specify different string parameter (filenames) to different instances. I have tried these code:

genvar i;
generate 
   for (i=0; i<2; i=i+1) begin:u
      rom #($sformatf("mif%d.mif",i)) U(
         //signals connected.
      );
   end
endgenerate

It is said that the code is not synthesizable. How can I specify variable string parameter in generate for block?

Answer 1

I had a similar problem but on a system that did not support $sformatf. My solution is a little dirty but may help others:

genvar i;
generate
  for (i=0; i<10; i=i+1)
  begin
    mymodule #(.NAME("NAME0" + i) instance(.RESET(mreset) ... );
  end
endgenerate

This works, I believe, by treating the string "NAME0" as a number (a 40-bit number). By adding i, you just increase the value by i and the result is the last ASCII char changes. Luckily '0' + i gives you '1', '2', '3' etc

The obvious flaw is this only works for 0-9, however there is a simple extension using divide and modulo arithmatic:

mymodule #(.NAME("NAME00" + (256 * (i / 10)) + (i % 10) ) ) ...

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As a side note, I ran into issues using string concatenation {"NAME", i} because Verilog was treating i as 32-bit value so the string ends up as:

NAME   1

due to the extra 'unwanted' 24 bits which equate to 3 null characters