hdl-util / hdmi

Star

Send video/audio over HDMI on an FPGA

audio video fpga intel xilinx vivado altera hdmi systemverilog dvi quartus hdlmake

Updated Jun 18, 2020
SystemVerilog

VLSI-EDA / PoC

Star

Open

Doc: Document installed Sphinx extensions, usable syntax, modifications

Paebbels commented Dec 18, 2016

The Sphinx documentation flow was extended by several sphinx and third party extensions. These extensions should be documented along with their modifications. A comprehensive syntax guide should be assembled, to collect all syntax notations at one place instead of dozens of third party documentation websites with partially poor usage descriptions.

Extensions list:

Standard Sphinx extensi

Doc: Document Python dependencies in the Quick Start Guide

Open

Doc: Document the change log from v0.0.0 until now

Find more good first issues →

f32c / f32c

Star

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

arduino fpga mips riscv xilinx altera lattice

Updated Jul 1, 2020
VHDL

olofk / edalize

Star

Open

Support resource information reporting from various backends

11

mithro commented Oct 10, 2019

Here is a simple example for Vivado.

https://github.com/SymbiFlow/fpga-tool-perf/blob/f8438d0447ae808fd1434073b037fa30b274c423/fpgaperf.py#L444-L506

    def vivado_resources(self):
        report_path = self.out_dir + "/" + self.project_name + ".runs/impl_1/top_utilization_placed.rpt"
        with open(report_path, 'r') as fp:
            report_data = fp.read()
            repo

README should have 1 or 2 line description of edalize

2

OpenFPGAduino / OpenFPGAduino

Star

All open source file and project for OpenFPGAduino project

nodejs javascript c iot arduino arm opensource fpga cpp hardware verilog blockly grove-shield iiot altera

Updated Oct 27, 2018
Makefile

pConst / basic_verilog

Star

Must-have verilog systemverilog modules

Updated May 22, 2020
Verilog

thinkoco / c5soc_opencl

Star

DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.

fpga opencl mandelbrot altera de1-soc vga sobel usb-cameras intelfpga de10-nano

Updated Jan 11, 2020
Verilog

drandyhaas / Haasoscope

Star

Docs, design, firmware, and software for the Haasoscope

python open-source fpga eagle open-hardware data-acquisition verilog oscilloscope altera

Updated Jun 12, 2020
Verilog

suoto / vim-hdl

Star

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

productivity pathogen vhdl vim-plugins verilog xilinx syntastic syntax-checker altera systemverilog trademarks vundle modelsim hdlcc-issue-tracker vimhdl-issue-tracker vim-hdl registered-trademarks

Updated Oct 28, 2019
Python

mithro / ixo-usb-jtag

Star

usb-jtag - Altera USB Blaster Emulation with a FX2

fpga xilinx altera usb-devices openocd jtag numato-opsis digilent-atlys cypress-fx2 ezusb digilent opsis numato urjtag

Updated Jun 29, 2020
C++

MohammedRashad / FPGA-Speech-Recognition

Star

Expiremental Speech Recognition System using VHDL & MATLAB.

fpga distance matlab vhdl speech-recognition signal pattern-recognition uart altera digital-signal-processing audio-processing hamming-distance euclidean-distances speech-recognition-engine domain-signals

Updated Mar 18, 2018
VHDL

HengRuiZ / from-key-array-to-the-LED-lattice

Star

fpga vhdl altera

Updated Aug 8, 2017
VHDL

capitanov / intfftk

Star

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

fpga dsp vhdl verilog fast-fourier-transform xilinx fft vivado altera cooley-tukey-fft digital-signal-processing fast-convolutions radix-2 integer-arithmetic route-optimization

Updated Apr 25, 2019
VHDL

VladisM / MARK_II

Star

Simple SoC in VHDL with full toolchain and custom board.

toolchain cpu fpga compiler vhdl assembler intel altera soc vbcc mark-ii max10

Updated Jun 4, 2018
VHDL

capitanov / fp23fftk

Star

Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).

fpga dsp matlab vhdl octave verilog fast-fourier-transform xilinx convolution fft altera cooley-tukey-fft floating-point digital-signal-processing fast-convolutions radix-2 frequency-analysis ieee754 chirp convolution-filter

Updated Jun 28, 2019
VHDL

robseb / rsyocto

Star

🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

Updated Jun 30, 2020
Python

delhatch / Spectrum

Star

Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action.

fpga audio-analysis verilog spectrum-analyzer fft altera rtaudio vga de2-115 vga-frame-buffer

Updated Feb 9, 2018
VHDL

thotypous / alterajtaguart

Star

Altera JTAG UART wrapper for Bluespec

bluespec uart usb-serial-adapters altera hardware-libraries jtag

Updated Mar 27, 2014
C

obiwanjacobi / Zalt

Star

Open

[SysCtrlr] Add help for terminal commands

obiwanjacobi commented Mar 8, 2020

More guiding help for the commands.

Add a help command that lists all commands
Provide help/details on parameters
Repeat (echo back) partial commands to let user finish it

dilshan / max2-audio-dac

Star

24-bit Stereo Audio DAC for Raspberry Pi

audio raspberry-pi altera cpld dac i2s-audio r-2r epm240t100c5n

Updated Jan 27, 2020
Verilog

sevvalmehder / 32-bit-MIPS-Processor

Star

A 32-bit MIPS processor used Altera Quartus II with Verilog.

register mips processor opcodes datapath altera quartus

Updated Sep 20, 2018
Verilog

stpe / jniosemu

Star

JNiosEmu is an educational Nios II based development environment and emulator with the purpose of making it easy to learn programming in assembler. Assemble your source with a single button click, immediately see how values change in a register or memory. All this without any prior knowledge of assembler programming or complex tool chains.

java emulator assembler altera nios

Updated Apr 1, 2018
Java

furrtek / DottoriLog

Star

Dottori-Kun for FPGA

video fpga logic arcade sega verilog altera jamma dottori-kun

Updated Aug 15, 2017
Verilog

orangeneko / redphone-pcb

Star

Simple handmade open source mobile phone

stm32 altera sim800 cyclone-iv mobile-phone

Updated Jun 17, 2020

Wissance / QuickSPI

Star

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

spi-interface fpga spi altera verilog-hdl xilinx-fpga xilinx-vivado verilog-components axi verilog-snippets spi-hdl spi-ip-core spi-pld spi-fpga verilog-spi axi-interfaces bit-oriented-spi soft-spi hard-spi dragster-spi

Updated Nov 21, 2017
Verilog

delhatch / Red_Tracker

Star

Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. See the video. Pure Verilog. (No soft-core processor.)

fpga image-processing verilog altera vga de2-115 vga-controller

Updated Jan 19, 2018
Verilog

capitanov / adc_configurator

Star

ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)

ddr dsp vhdl xilinx adc ddc altera dds digital-signal-processing fir jesd204b analog-signals serial-interface cic dac adc-configurator serdes-mode

Updated Aug 29, 2018
VHDL

OpenFPGAduino / fpga

Star

The fpga project for openFPGAdunino

fpga verilog altera qsys

Updated Feb 19, 2018
Verilog

thinkoco / de10-nano-riscv

Star

A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano

riscv altera risc-v intelfpga de10-nano

Updated Jan 7, 2020
C

robseb / HPS2FPGAmapping

Star

SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)

linux fpga python-script intel bootloader altera can-bus fpga-soc embedded-linux quartus-prime intel-fpga altera-fpga hps fpga-configuration soc-fpga fpga-fabric mapping-hps-peripherals rsyocto

Updated Jun 30, 2020
Verilog

altera

Here are 124 public repositories matching this topic...

hdl-util / hdmi

VLSI-EDA / PoC

Doc: Document installed Sphinx extensions, usable syntax, modifications

Doc: Document Python dependencies in the Quick Start Guide

Doc: Document the change log from v0.0.0 until now

f32c / f32c

olofk / edalize

Support resource information reporting from various backends

README should have 1 or 2 line description of edalize

OpenFPGAduino / OpenFPGAduino

pConst / basic_verilog

thinkoco / c5soc_opencl

drandyhaas / Haasoscope

suoto / vim-hdl

mithro / ixo-usb-jtag

MohammedRashad / FPGA-Speech-Recognition

HengRuiZ / from-key-array-to-the-LED-lattice

capitanov / intfftk

VladisM / MARK_II

capitanov / fp23fftk

robseb / rsyocto

delhatch / Spectrum

thotypous / alterajtaguart

obiwanjacobi / Zalt

[SysCtrlr] Add help for terminal commands

dilshan / max2-audio-dac

sevvalmehder / 32-bit-MIPS-Processor

stpe / jniosemu

furrtek / DottoriLog

orangeneko / redphone-pcb

Wissance / QuickSPI

delhatch / Red_Tracker

capitanov / adc_configurator

OpenFPGAduino / fpga

thinkoco / de10-nano-riscv

robseb / HPS2FPGAmapping

Improve this page

Add this topic to your repo