PaddlePaddle/Paddle使用git-flow分支模型，切换的issue：PaddlePaddle/Paddle#250 ，文档中亦有对PaddlePaddle分支规范的介绍。

PaddlePaddle的主版本库遵循git-flow分支规范。其中:

• master分支为稳定(stable branch)版本

Solutions

1. Convert INO files to CPP

2. Manual prototype declaration

#ifdef DO_NOT_USE
typedef int32_t delaytype;
void thisShouldNotAppearInTheBinary(delaytype timer); // aded manually
void thisShouldNotAppearInTheBinary(delaytype timer) {
  delay(timer);
}
#endif

Collect coverage information at end of tests.

https://www.veripool.org/projects/verilator/wiki/Manual-verilator

1. Pass --coverage option to verilator in makefile
2. Modify c++ test harness to VerilatedCov::write into an output file. There will be one file per test, which should be collected somewhere (this probably needs to be done by test_harness.py)
3. Run verilator_coverage executable,

What would be workflow for creating and installing external haskell packages? I am running snap from release 1.2. I used to work with cabal in past, but I am out of loop on current packet management in new environment.

Any pointers would be much appreciated.

This is the first RISCV core I've been able to get up and running without breaking my head. Much appreciation for the SpinalHDL team for the making this work with Qsys and Avalon. :) (Although SpinalHDL itself puzzling still.)

Where should notes and documentation go? (Is there a wiki?) There's a lot of little things I had to figure out. It would be nice to make it easy to post the notes. One ex

I would like to use icestudio in class e.g. to demonstrate the simulation of logic gates. Ultimatively I would like to create logic tables with the students.

I found following two descriptions but - unfortunately - do not speak spanish:

• https://groups.google.com/forum/#!topic/fpga-wars-explorando-el-lado-libre/E-EwTaCl01Q
• http://haudahau.com/vadedos/?p=1497 also after using google transla

If this is not the case a page fault should be generated. Right now we generate an instruction access fault.

https://github.com/pulp-platform/ariane/blob/ad70ce1f30dad539e5a365ffe71a02aaf20b397e/src/load_store_unit.sv#L339

Appears to be a python3.7 package installation problem?
ubuntu 18.04 LTS
python3.7
glasgow repo cloned today

After following the install instructions I try to run glasgow and get the following:

480s:2000: cd ~/.local/bin/
T480s:2001: ./glasgow 
Traceback (most recent call last):
  File "./glasgow", line 11, in <module>
    load_entry_point('glasgow', 'console_scripts', 'glasgow')

Auto-generated files
.vscode/c_cpp_properties.json
.vscode/launch.json
contains absolute path, for example:

"configurations": [
        {
            "type": "platformio-debug",
            "request": "launch",
            "name": "PIO Debug",
            **"executable": "/Users/username/Projects/projname/.pio/build/esp32dev/firmware.elf",
            "toolchainBinDir": "/Users/u

FuseSoC supports use flags, but doesn't document which use flags are actually set. This needs to be documented.

Currently we set:

• A target use flag target_TARGETNAME, e.g. target_sim if fusesoc is called with --target=sim.
• A tool use flags tool_TOOLNAME, e.g. tool_verilator if fusesoc is called with --tool=verilator

Support for user-defined use flags is being developed in #26

Just spent about half an hour trying to figure out how to use and/or install the Library Manager gui into the IDE My IDE (2.0 beta 2) doesn't match the docs in a handful of places. Specifically, the following imply that there is a Library Manager gui, which one might assume has to be installed separately:

• "Library Manager" is listed in th

grep unknown opentitan.fasm  | wc
    557    6127   52651

557 bits isn't too many. Most of these are likely related to the DSP, as 1 DSP is being used:

DSP_L_X66Y110.DSP48.DSP_0.AREG_0
DSP_L_X66Y110.DSP48.DSP_0.BREG_0
DSP_L_X66Y110.DSP48.DSP_0.MASK[45:0] = 46'b1111111111111111111111111111111111111111111111
DSP_L_X66Y110.DSP48.DSP_0.ZADREG[0]
DSP_L_X66Y110.DSP48.DSP_0.ZAL

The README says:

[...] you'll need an SD card image for your DE10 with a valid installation of Cascade. Cascade can generate this image for you automatically [...]

The obvious question is "how". Is there a command that generates the image?

I have a working DE Nano, it has linux running, it is connected through the Ethernet.
Is this image not sufficient, and Cascade should generate

VUnit.add_source_files_from_csv() only passes vhdl_standard kwarg to Library.add_source_file(). However, my file gatherer uses .ahd file extensions to denote altera, .xhd to denote xilinx, and so on. I need the file_type available at least so I can tell VUnit that those file types are still vhdl, but all arguments should be available.

Expected Behaviour

Odin should compare the titles by name and make sure they match. Also be case sensitive (which I think odin is).

Current Behaviour

Odin uses strcmp thus comparing the names and blank spaces not the tokens.

Possible Solution

Compare the tokens instead of using strcmp

Steps to

The TornadoVM repository contains a module with several examples. Include more use cases for acceleration with TornadoVM, such as a graphical version for NBODY, filter for photography, block-chain. etc.

This is already possible through the API, but we should also expose it through hls4ml tool. So the user would specify his implementation of a layer, a config and function call template and the C++ code.