Enabling Intel Graphics multi-sample anti-aliasing (Use Application Settings) will cause VeloView point cloud view become blank. VeloView will only work normal if disable/turn off the multi-sample anti-aliasing. Tested version is 3.5.3-36-g9e4f067. However, official version 3.5.0 work perfectly either enable or disable the anti-aliasing.

![Intel_EnabledAntiAliasing](https://user-images.githubus

Executing the following snippet

from nmigen import *
from nmigen.back import verilog

class WrappedInstance(Elaboratable):
    def __init__(self):
        self.a = Signal()
        self.b = Signal()

    def elaborate(self, _):
        m = Module()
        m.submodules += Instance("test", o_aout = self.a, o_bout = self.b)
        return m

m = Module()
m.submodules.instan

A couple people have asked for a easy way to change/update the root password without having to recompile the entire image.

Saving ROOTPASSWORD with fw_setenv, and using that might be an easy way?

Vendor tools dram tests were not enabled until #1234 got merged.

With SymbiFlow/symbiflow-arch-defs#1268 I have temporarily disabled the vivado_targets, to let CI go green (as it has been red for too long now).

This issue is to keep track of the problem with DRAM evaluated on vendor tools with fasm2bels.

Currently we need to create a verilog from a graph before we can run lgcheck.
Ideally, lgcheck should work with both verilog and lgraphs (or a mix of both).

Also, in case where formality is needed, it should create a tmp verilog automatically.

Add command line option, to enable the user to choose which builder he/she wants to use. Suggestion:
--builder BUILDER specify the builded to be used

By adding it, it would allow:

1. Users to actively choose the builder the way to use, without any code change (e.g. editing hdl_checker/builder_utils.py).
2. to separate use cases and make it easier to track bugs that may arise.

Similar to CBOLD's ^ operator.

Instead of:
vcc << R(to=C(to=gnd))
We could have:
vcc ^ R() ^ C() ^ gnd

As this project is mainly addressed for SystemVerilog and commercial tools users to encourage them to abandon the sinking ship, it is good to provide a more informative examples and tutorials. The goal is to show consistency with SystemVerilog coverage/randomization features with much higher flexibility and user-friendliness.
Also @cmarqu provided an interesting tutorial: https://www.divio.com/b