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chisel3
Here are 60 public repositories matching this topic...
Open-source high-performance RISC-V processor
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Jun 19, 2021 - Scala
Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
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Jun 25, 2020 - Scala
Provides dot visualizations of chisel/firrtl circuits
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May 28, 2021 - Scala
vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
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Apr 6, 2020 - Scala
Quasar 2.0: Chisel equivalent of SweRV-EL2
scala
processor
chisel
riscv
rtl
chisel3
open-source-hardware
verilator
asic-verification
axi4
ahb-lite
asic-design
swerv
swerv-el2
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Apr 13, 2021 - Scala
『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
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Jul 30, 2019 - Scala
A caravan equipped with API for creating bus protocols in Chisel with ease.
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Jun 2, 2021 - Scala
Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)
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Dec 16, 2019 - Scala
Brainfxxk Processor written Scala(Chisel)
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Mar 25, 2019 - Verilog
A configurable processing element for deep neural network accelerators
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Sep 22, 2018 - Scala
A chisel3 wrapper for pulp-platform/fpnew
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Apr 10, 2020 - SystemVerilog
Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"
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Jul 30, 2019 - Scala
A Scala w/ Chisel based implementation of a processing engine generator for neural network accelerators.
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Aug 16, 2018 - Jupyter Notebook
Systolic-array based Deep Learning Accelerator generator
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Dec 11, 2020 - Verilog
This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)
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Jun 8, 2021 - Scala
Constraint Random Verification For Chisel3
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Jan 3, 2021 - Scala
Cryptography accelerator core (for AES128/AES256 and SHA256) designed in Chisel3, primarily targeting ASIC platforms.
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Jan 11, 2021 - Scala
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I have been experimenting with replacing the old
Enums with the newChiselEnuminrocket-chip. One important function that is used a lot, but missing fromChiselEnumisisOneOf. This should be fairly straight forward to implement in a type-safe manner.