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rocket-chip
Here are 17 public repositories matching this topic...
SonicBOOM: The Berkeley Out-of-Order Machine
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Jul 16, 2020 - Scala
FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud
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Jul 18, 2020 - Scala
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
boom
rocket
rocket-chip
chip-generator
chisel
riscv
rtl
peripherals
soc
out-of-order
superscalar
risc-v
firesim
accelerators
chipyard
hwacha
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Jul 17, 2020 - C
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
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Jan 23, 2020 - Scala
RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
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Nov 14, 2018 - SystemVerilog
Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.
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Nov 24, 2019 - C
C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
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Jul 14, 2020 - C
A fault-injection framework using Chisel and FIRRTL
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Sep 4, 2018 - Scala
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
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Jan 30, 2020 - Tcl
A simple baremetal program template for RISC-V inspired from riscv benchmark tests
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Apr 17, 2018 - C
Parallella RISC-V Prebuilt Images
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Aug 18, 2016
Network components (NIC, Switch) for FireBox
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Jul 13, 2020 - Scala
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Jun 28, 2020 - Scala
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