UC Berkeley Architecture Research

Repositories

• gemmini-rocc-tests

  Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
  C 11 11 1 1 Updated Jul 18, 2020

• chipyard

  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

  boom rocket rocket-chip chip-generator chisel riscv rtl
  C BSD-3-Clause 178 264 46 (3 issues need help) 11 Updated Jul 17, 2020

• riscv-sodor

  educational microarchitectures for risc-v isa
  Scala 106 346 10 0 Updated Jul 16, 2020

• gemmini

  Berkeley's Systolic Array Generator
  Scala 16 69 3 1 Updated Jul 15, 2020

• testchipip
  Scala BSD-3-Clause 26 23 8 6 Updated Jul 11, 2020

• chisel-repo-tools

  Tools (mostly python3.7, but some python2.7) for accessing GitHub repos via GitHub API
  Python 0 0 0 0 Updated Jul 10, 2020

• hammer

  HAMMER: Highly Agile Masks Made Effortlessly from RTL
  Python BSD-3-Clause 23 83 189 (1 issue needs help) 13 Updated Jul 7, 2020

• esp-isa-sim

  Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project
  C 10 2 1 2 Updated Jul 7, 2020

• berkeley-hardfloat
  Scala 49 104 12 4 Updated Jul 7, 2020

• barstools

  Useful utilities for BAR projects
  Scala BSD-3-Clause 7 14 20 4 Updated Jul 4, 2020

• chisel-release

  Chisel release tooling
  Makefile BSD-3-Clause 2 0 1 0 Updated Jun 29, 2020

• esp-tests

  Custom extensions to the RISC-V tests for the UCB-BAR ESP project
  C 4 1 0 1 Updated Jun 28, 2020

• chisel-testers2

  Repository for chisel3 testers2 open alpha
  Scala 19 40 52 (1 issue needs help) 16 Updated Jun 28, 2020

• dsptools

  A Library of Chisel3 Tools for Digital Signal Processing
  Scala BSD-3-Clause 20 92 34 6 Updated Jun 25, 2020

• ariane-wrapper

  Wrapper for ETH Ariane Core
  Scala 1 8 0 1 Updated Jun 24, 2020

• nvdla-workload

  Base NVDLA Workload for FireMarshal
  Shell 1 2 2 (1 issue needs help) 0 Updated Jun 19, 2020

• nvdla-wrapper

  Wraps the NVDLA project for Chipyard integration
  Verilog 1 1 0 1 Updated Jun 11, 2020

• chisel-gui

  A prototype GUI for chisel-development
  Scala BSD-3-Clause 6 29 1 1 Updated Jun 9, 2020

• sha3
  Verilog 10 34 0 0 Updated Jun 5, 2020

• chisel-tutorial

  chisel tutorial exercises and answers
  Scala 140 359 25 1 Updated Jun 4, 2020

• libgloss-htif

  A libgloss replacement for RISC-V that supports HTIF
  C 3 0 1 0 Updated Jun 4, 2020

• nvdla-sw

  Forked from nvdla/sw

  NVDLA SW adjusted for FireSim Linux Simulations
  C++ 122 0 0 0 Updated May 29, 2020

• spec2017-workload

  FireMarshal workload for SPEC2017
  Makefile 2 1 1 0 Updated May 26, 2020

• esp-binutils-gdb

  ESP toolchain binutils port
  C 1 0 3 0 Updated May 16, 2020

• esp-opcodes

  Custom extensions to the RISC-V opcodes for the UCB-BAR ESP project
  TeX 1 0 0 0 Updated May 8, 2020

• block-inclusivecache-sifive

  Forked from sifive/block-inclusivecache-sifive
  Scala Apache-2.0 12 0 0 0 Updated May 5, 2020

• hwacha

  Microarchitecture implementation of the decoupled vector-fetch accelerator
  Scala 14 49 6 2 Updated Apr 30, 2020

• riscv-blas

  Custom BLAS and LAPACK Cross-Compilation Framework for RISC-V
  Fortran 3 7 0 0 Updated Apr 26, 2020

• autophase
  Python BSD-3-Clause 1 3 0 0 Updated Apr 21, 2020

• chisel-awl
  Scala 1 9 8 2 Updated Apr 3, 2020