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risc

Here are 99 public repositories matching this topic...

rv8-io / rv8

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Open

Add output buffering, labels, relocation and execution to the JIT API

michaeljclark commented Sep 24, 2016

The JIT API currently just checks instruction operands and emits the instruction.

Add simple buffer implementation to collect JIT output
Add support for labels, and link step
Add mprotect handling (W^X) so output JIT can be executed
Add host ABI trampoline for calling JIT with arguments and return value

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Open

Add support for multiple extensions in opcodes e.g. RVC FPU instructions

Ripes

mortbopet / Ripes

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Add instruction formats to assembly error tooltip

mortbopet commented Oct 8, 2018

For instance, if a user tries to write jalr x0 0(x1) the tooltip should also state that jalr has the format
jalr [rd] [rs] [imm].

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Jupiter

andrescv / Jupiter

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RISC-V Assembler and Runtime Simulator

education simulator assembler riscv risc risc-v riscv-asm rv32 rv32imf riscv-simulator runtime-simulator

Updated Oct 29, 2019
Java

chipsalliance / Cores-SweRV

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SweRV EH1 core

fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design swerv swerv-eh1

Updated Jun 26, 2020
SystemVerilog

kvakil / venus

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RISC-V instruction set simulator built for education

education frontend backend assembler risc risc-v venus

Updated Jan 5, 2019
Kotlin

mrisc32 / mrisc32

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Open

Documentation: Write proper instruction documentation

mbitsnbites commented Dec 11, 2019

Right now the best documentation of MRISC32 instructions is given in:

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Open

Consider trading conditional branch ranges for more type D instructions

Wren6991 / RISCBoy

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Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

cpu fpga gameboy pcb risc risc-v

Updated May 12, 2020
Verilog

michaeljclark / riscv-meta

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RISC-V Instruction Set Metadata

metadata riscv risc risc-v

Updated Oct 21, 2018

SuperJMN / Plotty

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C language compiler from scratch for a custom architecture, with virtual machine and all

c emulator parser csharp parsing compiler uwp virtual-machine net risc c-language superpower

Updated May 13, 2018
C#

Mariotti94 / WebRISC-V

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WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]

php education processor-architecture simulator pipeline assembly computer-architecture risc risc-v pipeline-simulation-environment

Updated Jun 19, 2020
PHP

lxp32 / lxp32-cpu

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A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

cpu fpga vhdl risc wishbone soft-core risc-processor wishbone-bus risc-cpu

Updated Feb 25, 2019
Assembly

MaxXSoft / Uranus

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Uranus MIPS processor by MaxXing & USTB NSCSCC team

cpu fpga mips verilog risc

Updated Dec 14, 2019
Verilog

bitmario / RISVM

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A low overhead, embeddable bytecode virtual machine in C++

vm interpreter bytecode cpp virtual-machine asm assembler risc bytecode-interpreter

Updated Dec 25, 2018
C++

liuqidev / 8-bits-RISC-CPU-Verilog

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Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。

cpu fsm verilog risc

Updated Jan 20, 2019
Verilog

Vulcan

vmmc2 / Vulcan

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RISC-V Instruction Set Simulator (Built for education).

education simulator assembly computer-architecture risc risc-v

Updated Jun 26, 2020
Dart

lite-david / comet

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RISC-V ISA based 32-bit processor written in HLS

asic fpga hls comet isa vivado risc catapult

Updated Nov 7, 2019
C

platformio / platform-shakti

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Shakti: development platform for PlatformIO

platformio riscv risc risc-v platformio-platform

Updated Jun 25, 2020
Python

BigEd / XSOC-xr16

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System-on-a-Chip for FPGA, with xr16 RISC core and LCC port

cpu fpga risc system-on-chip 16bit non-commercial-license revocable-license

Updated Jul 23, 2017
C

KPU-RISC / KPU

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KPU - the RISC based Open Source CPU

cpu compiler assembler osdev risc cpu-emulator

Updated Nov 4, 2017
C#

wyvernSemi / mico32

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LatticeMico32 instruction set simulator project

linux c-plus-plus embedded fpga processor gdb iss python3 tcp-socket debug tkinter risc cpu-model 32-bits soft-core serial-communication latticemico32 com0com

Updated Sep 30, 2018
C++

ulx3s / ulx3s.github.io

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community projects that can be used with the ULX3S FPGA ESP32 board

fpga vhdl verilog risc ecp5 ulx3s emard

Updated Mar 28, 2020

digital-design-snu / ANPPV_RISC_PipelinedProcessor

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pipeline processor architecture verilog vivado risc

Updated Apr 8, 2017
Verilog

risc

whzup / risc

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💻

🍁 A design for a RISC

vhdl hardware-architectures risc

Updated May 28, 2019
VHDL

djzenma / RV32IC-CPU

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Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.

cpu verilog risc hdl pipeline-processor verilog-hdl risc-v rv32i verilog-snippets pipeline-cpu risc-processor riscv32 riscv-simulator rv32imc verilog-code riscv32im

Updated May 29, 2020
Verilog

mrisc32 / mrisc32-a1

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A pipelined, in-order, scalar implementation of the MRISC32 ISA

cpu vhdl risc soft-core fpu mrisc32

Updated Jun 19, 2020
VHDL

DrItanium / syn

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Multi target processor simulator

simulator cpu templates cpp14 virtual risc synthetic clips cisc

Updated Mar 25, 2018
C

zambonin / r2000

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Solutions for Patterson & Hennessy, fourth edition.

pipeline mips cache isa risc plaintext ufsc computer-organization

Updated Apr 9, 2017

furkankayar / DEUARC

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DEUARC RISC computer design in Quartus II 13.0

processor-architecture risc quartus2

Updated Feb 23, 2020
VHDL

dominiksalvet / risc64-m1

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💻 Pipelined RISC64 microarchitecture.

open-source cpu pipeline hardware processor vhdl rtl implementation risc hdl 64-bit microarchitecture risc64

Updated Jun 24, 2020

michaelrios28 / 16-bit-risc-processor

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A 16-bit Reduced Instruction Set Computing(RISC) processor capable of fetching and executing a set of 16-bit machine instructions.

fpga verilog risc artix-7

Updated Oct 1, 2017
Verilog

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