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@IBM @PSML @bu-icsg @freechipsproject
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Pinned

  1. Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

    Scala 143 29

  2. Repository for basic (and not so basic) Verilog blocks with high re-use potential

    Verilog 221 79

  3. Tests for example Rocket Custom Coprocessors

    C 38 17

  4. C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)

    C 26 10

  5. A fault-injection framework using Chisel and FIRRTL

    Scala 20 9

  6. Major mode for editing FIRRTL files in Emacs

    Emacs Lisp 1 4

1,044 contributions in the last year

Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Jan Mon Wed Fri

Contribution activity

January 2020

Created a pull request in freechipsproject/chisel3 that received 3 comments

Emit FIRRTL andr, orr for Bits.{andR, orR}

Change the emission strategy for Bits methods andR and orR to emit FIRRTL bitwise reduce operations andr and orr. The CHIRRTL emission strategy for…

+6 −6 3 comments

Created an issue in freechipsproject/www.chisel-lang.org that received 1 comment

List Projects Using Chisel

It would be good to provide a list of the (large) number of projects using Chisel. See discussion here: https://groups.google.com/forum/#!topic/chi…

1 comment
11 contributions in private repositories Jan 3 – Jan 25

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