ZAP : A v5TE Superpipelined ARM Processor with Caches, MMUs and TLBs (140MHz @ Artix-7 FPGA)
arm
cpu
fpga
pipeline
zap
cache
processor
architecture
assembler
computer
rtl
verilog
microprocessor
systemverilog
gplv2
mmu
softprocessor
writeback-cache
artix-7
armv5te
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Updated
Jun 12, 2022 - SystemVerilog