#
vivado
Here are 224 public repositories matching this topic...
An abstraction library for interfacing EDA tools
fpga
simulation
vhdl
eda
verilog
xilinx
synthesis
vivado
altera
systemverilog
icestorm
lattice
icarus-verilog
modelsim
ghdl
yosys
verilator
riviera-pro
fossi
spyglass
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Updated
Aug 8, 2020 - Python
FPGA Accelerator for CNN using Vivado HLS
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Updated
Nov 29, 2019 - C++
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
cmake
asic
fpga
cpp
verification
rtl
verilog
xilinx
vivado
systemverilog
systemc
unit-tests
hdl
modelsim
uvm
verilator
quartus
testing-rtl
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Updated
Nov 25, 2019 - SystemVerilog
Build Customized FPGA Implementations for Vivado
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Updated
Aug 7, 2020 - Java
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
linux
iot
fpga
zynq
tensorflow
assembly
vhdl
embedded-systems
internet-of-things
hardware-architectures
verilog
xilinx
vivado
tensor
hardware-designs
hardware-acceleration
fpga-accelerator
hardware-description-language
ip-core
tpu
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Updated
Jan 5, 2019 - VHDL
Verilog HDL/SystemVerilog support for VS Code
ctags
vscode
verilog
vivado
systemverilog
modelsim
verilog-hdl
iverilog
verilator
language-server-client
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Updated
Aug 8, 2020 - TypeScript
Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
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Updated
Jul 17, 2020 - Tcl
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
fpga
dsp
vhdl
verilog
fast-fourier-transform
xilinx
fft
vivado
altera
cooley-tukey-fft
digital-signal-processing
fast-convolutions
radix-2
integer-arithmetic
route-optimization
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Updated
Apr 25, 2019 - VHDL
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
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Updated
Jan 30, 2020 - Tcl
Verilog Implementation of an ARM LEGv8 CPU
arm
verilog
xilinx
isa
vivado
hazard-detection
ldr
pipeline-cpu
single-cycle
hennessy
patterson
legv8-arm
multi-cycle
arm-legv8-simulator
forwarding-unit
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Updated
Oct 3, 2018 - Verilog
mirror of https://git.elphel.com/Elphel/vdt-plugin
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Updated
Nov 29, 2017 - Java
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
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Updated
Jul 21, 2020 - SystemVerilog
Lenet for MNIST handwritten digit recognition using Vivado hls tool
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Updated
Jul 22, 2020 - Objective-C
a project to check the FOSS synthesizers against vendors EDA tools
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Updated
May 18, 2020 - Makefile
Global Dark Mode for ALL apps on ANY platforms.
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Updated
Jul 21, 2020 - Verilog
16-bit Adder Multiplier hardware on Digilent Basys 3
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Updated
Aug 1, 2020 - Verilog
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