Solutions

1. Convert INO files to CPP

2. Manual prototype declaration

#ifdef DO_NOT_USE
typedef int32_t delaytype;
void thisShouldNotAppearInTheBinary(delaytype timer); // aded manually
void thisShouldNotAppearInTheBinary(delaytype timer) {
  delay(timer);
}
#endif

Appears to be a python3.7 package installation problem?
ubuntu 18.04 LTS
python3.7
glasgow repo cloned today

After following the install instructions I try to run glasgow and get the following:

480s:2000: cd ~/.local/bin/
T480s:2001: ./glasgow 
Traceback (most recent call last):
  File "./glasgow", line 11, in <module>
    load_entry_point('glasgow', 'console_scripts', 'glasgow')

FuseSoC supports use flags, but doesn't document which use flags are actually set. This needs to be documented.

Currently we set:

• A target use flag target_TARGETNAME, e.g. target_sim if fusesoc is called with --target=sim.
• A tool use flags tool_TOOLNAME, e.g. tool_verilator if fusesoc is called with --tool=verilator

Support for user-defined use flags is being developed in #26

grep unknown opentitan.fasm  | wc
    557    6127   52651

557 bits isn't too many. Most of these are likely related to the DSP, as 1 DSP is being used:

DSP_L_X66Y110.DSP48.DSP_0.AREG_0
DSP_L_X66Y110.DSP48.DSP_0.BREG_0
DSP_L_X66Y110.DSP48.DSP_0.MASK[45:0] = 46'b1111111111111111111111111111111111111111111111
DSP_L_X66Y110.DSP48.DSP_0.ZADREG[0]
DSP_L_X66Y110.DSP48.DSP_0.ZAL

The SCons file is quite "magical" and undocumented at the moment. I needed to find it to understand these points for example:

• how is a PCF file located? which is chosen if there are multiple?
• how are testbench files recognized and treated?
• how are verilog source files recognized and treated?

IMO the second two should be documented in the docs for apio sim and apio build respectiv

FER2013 is the dataset for Face Expression Recognition.
7 class classification.

It's looks better for tutorial than CIFAR10.

https://www.kaggle.com/c/challenges-in-representation-learning-facial-expression-recognition-challenge/data

Executing the following snippet

from nmigen import *
from nmigen.back import verilog

class WrappedInstance(Elaboratable):
    def __init__(self):
        self.a = Signal()
        self.b = Signal()

    def elaborate(self, _):
        m = Module()
        m.submodules += Instance("test", o_aout = self.a, o_bout = self.b)
        return m

m = Module()
m.submodules.instan

Here is a simple example for Vivado.

https://github.com/SymbiFlow/fpga-tool-perf/blob/f8438d0447ae808fd1434073b037fa30b274c423/fpgaperf.py#L444-L506

    def vivado_resources(self):
        report_path = self.out_dir + "/" + self.project_name + ".runs/impl_1/top_utilization_placed.rpt"
        with open(report_path, 'r') as fp:
            report_data = fp.read()
            repo

to help with unit tests, be able to turn off the text on the patterns. This will provide known image for testing inputs, testing loopback, and testing outputs (like the encoder).

I can see a case for leaving some of it on, but I would prefer the option of having the same image across all everythings. The case for testing for text on an image doesn't seem worth the effort in providing a UI/A

Vendor tools dram tests were not enabled until #1234 got merged.

With SymbiFlow/symbiflow-arch-defs#1268 I have temporarily disabled the vivado_targets, to let CI go green (as it has been red for too long now).

This issue is to keep track of the problem with DRAM evaluated on vendor tools with fasm2bels.

FASM itself doesn't understand the feature names, but for consistency between projects we should have a style guide for them.