If this is not the case a page fault should be generated. Right now we generate an instruction access fault.

https://github.com/pulp-platform/ariane/blob/ad70ce1f30dad539e5a365ffe71a02aaf20b397e/src/load_store_unit.sv#L339

Summary:
A nice-to-have feature is the ability to enable and disable hardware features from the software.

Examples:

• Enable TSO memory consistency
• Enable watchdog timer
• Change predictor behaviors

High-level thoughts:

• Do not use non-standard Control/Status Registers (CSRs). The address space will get too congested, not indexable, messy to assemble for, etc.
• Inst

This is not strictly related to CV32E40P as the problem seems to be in fpnew, but did anybody verify the operation of CV32E40P with fpnew in verilator?

There is a coding-style in fpnew, which prevents verilator to work. But even if this problem is solved, the simulation is not running due to a deadlog in the div_sqrt unit. The same code runs with Questa/Modelsim without problems!?

It is hard

I found two issues with breakpoints while playing around with timertool for #80.

1. Changing a breakpoint does not have an affect on a running program until it is paused and then restarted. Breakpoints are passed to the simulator thread as function arguments (which is definitely necessary), but that means changes to the UI do not affect the simulator until the threads is shut down and restarted.